• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.61-68
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• 2008

This paper introduces an embedded core test wrapper for AMBA based System-on-Chip(SoC) test. The proposed test wrapper is compatible with IEEE 1500 and can be controlled by ARM Test Interface Controller(TIC). We use IEEE 1500 wrapper boundary registers as temporal registers to load test results as well as test patterns and apply a modified scan test procedure. Test time is reduced by simultaneously performing primary input insertion and primary output observation as well as scan-in and scan-out.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.1
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• pp.55-62
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• 2016

In this paper, we propose a hybrid multi.system-on-chip (H-MSoC) architecture that provides a high-flexibility system in a rapid development time. The H-MSoC approach provides a flexible system-on-chip (SoC) architecture that is easy to configure for physical- and application-layer development. The physical- and application-layer aspects are dynamically designed and modified; hence, it is important to consider a design methodology that supports rapid SoC development. Physical layer development refers to intellectual property cores or other modular hardware (HW) development, while application layer development refers to user interface or application software (SW) development. H-MSoC is built from multi-SoC architectures in which each SoC is localized and specified based on its development focus, either physical or application (hybrid). Physical HW development SoC is referred to as physical-SoC (Phy-SoC) and application SW development SoC is referred to as application-SoC (App-SoC). Phy-SoC and App-SoC are connected to each other via Ethernet. Ethernet was chosen because of its flexibility, high speed, and easy configuration. For prototyping, we used a LEON3 SoC as the Phy-SoC and a ZYNQ-7000 SoC as the App-SoC. The proposed design was proven in real-time tests and achieved good performance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.175-183
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• 2014

In this paper, we present the design and implementation of real-time sound localization based on $0.13{\mu}m$ CMOS process. Time delay of arrival (TDOA) estimation was used to obtain the direction of the sound signal. The sound localization chip consists of four modules: data buffering, short-term energy calculation, cross correlation, and azimuth calculation. Our chip achieved real-time processing speed with full range ($360^{\circ}$) using three microphones. Additionally, we developed a dedicated sound localization circuit (DSLC) system for measuring the accuracy of the sound localization chip. The DSLC system revealed that our chip gave reasonably accurate results in an experiment that was carried out in a noisy and reverberant environment. In addition, the performance of our chip was compared with those of other chip designs.

• Journal of the Korean Society for Precision Engineering
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• v.7 no.2
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• pp.85-94
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• 1990

In automatic metal cuttings, the chip control is one of the serious problems. So the automatic detection of chip forms is essential to the chip control in automatic metal cuttings. Cutting experiments were carried out under the variety of cutting conditions (cutting speed, feed, depth of cut and tool geometry) and with workpiece made of steel (S45C), and cutting forces were measured in-processing by using a piezoelectric type Tool Dynamometer. In this report, the frequency analysis of dynamic components, the upper frequency distributions, the ratio of RMS values, the numbers of null point and the probability density were calculated from the dynamic componeents of cutting forces filtered through various band pass filters. Experimental results showed that computer chip form monitoring system based on the cutting forces was designed and simulated and that 6 type of chip forms could be detected while in-process machining.

• Proceedings of the Korean Society of Veterinary Pathology Conference
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• 2003.10a
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• pp.32-32
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• 2003

Intestinal infections are common in growing pigs and can be caused by multiple pathogens, environmental and management factors [1]. Among the most important viruses in swine enteritis are porcine epidemic diarrhea virus (PEDV), transmissible gastroenteritis virus (TGEV), porcine enteric calicivirus (PECV), porcine group A rotavirus (PRV gp A) and bacteria are Escherichia coli and Salmonella spp. and protozoa is Isospora suis [1]. The DNA chip system can serve as a powerful tool that can be utilized for simultaneous detection of specific pathogenic bacteria strains and viruses [2,3]. The combination of PCR and DNA chip technology will provide a novel method for the detection of porcine enteric pathogens thus revolutionize the diagnosis and management of the disease. The aim of this study is to develop DNA chip system for the rapid and reliable detection of five major porcine enteric pathogens based on oligonucleotide DNA chip hybridization. (omitted)

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.6
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• pp.1128-1133
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• 2008

Context-aware computing has been attracting the attention as an approach to alleviating the inconvenience in human-computer interactions. This paper proposes a context-aware system architecture to be implemented on an UoC (Ubiquitous system on Chip). A new proposed technology of CRS (Context Recognition Switch) and DOS (Dynamic and Optimal Standard) based on Context-awareness system architecture with pre-processor, HPSP(High Performance Signal Processor) in this paper. And proposed a new algorithm using in network topology processor shows for Ubiquitous Computing System. implementing in UoC (Ubiquitous System on Chip) base on the IEEE 802.15.4 WPAN (Wireless Personal Area Network) standard. Also, This context-aware based UoC architecture has been developed to apply to mobile intelligent robots which would support human in a context-aware manner.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.193-196
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• 2001

One of the major reasons for not integrating a VCO on one-chip in a PLL (phase locked loop) system is the large chip-to-chip variation of the VCO (voltage controlled oscillator) center frequency. In this thesis, a simple bias technique is proposed to compensate the process fluctuation. The proposed bias technique is applied to the VCO and it reduces the deviation of the VCO center frequency from 35% to 8 %. With the suggested bias technique, a 400 MHz frequency synthesizer is designed for general purpose. It utilizes a programmable divider for various division ratio. The design methodology provides the possibility of the one-chip solution for a PLL system.

• ETRI Journal
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• v.28 no.4
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• pp.525-528
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• 2006

In this letter, we present a design of a single chip video decoder called advanced mobile video ASIC (A-MoVa) for mobile multimedia applications. This chip uses a mixed hardware/software architecture to improve both its performance and its flexibility. We designed the chip using a partition between the hardware and software blocks, and developed the architecture of an H.264 decoder based on the system-on-a-chip (SoC) platform. This chip contains 290,000 logic gates, 670,000 memory gates, and its size is $7.5\;mm{\times}7.5\;mm$ (using 0.25 micron 4-layers metal CMOS technology).

• ETRI Journal
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• v.35 no.2
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• pp.301-310
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• 2013

Nowadays, the multicore processor is watched with interest by people all over the world. As the design technology of system on chip has developed, observing and controlling the processor core's internal state has not been easy. Therefore, multicore processor debugging is very difficult and time-consuming. Thus, we need a reliable and efficient debugger to find the bugs. In this paper, we propose an on-chip debug architecture for multicore processors that is easily adaptable and flexible. It is based on the JTAG standard and supports monitoring mode debugging, which is different from run-stop mode debugging. Compared with the debug architecture that supports the run-stop mode debugging, the proposed architecture is easily applied to a debugger and has the advantage of having a desirable gate count and execution cycle. To verify the on-chip debug architecture, it is applied to the debugger of the prototype multicore processor and is tested by interconnecting it with a software debugger based on GDB and configured for the target processor.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.1663-1667
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• 2003

This thesis is on tile development of LD(Laser Diode) chip tester and the control system based on graphical programming language(LabVIEW) to control the equipment. The LD chip tester is used to test the optic power and the optic spectrum of the LD Chip. The emitter size of LD chip and the diameter of the receiver(optic fiber) are very small. Therefore, in order to test each chip precisely, this tester needs high accuracy. However each motion part of the tester could not accomplish hish accuracy due to the limit of the mechanical performance. Hence. an image processing with machine vision was carried out in order to compensate for the error. and also a load test was carried out so as to reduce tile impact of load on chip while the probing motion device is working. The obtained results were within ${\pm}$5$\mu\textrm{m}$ error.