• 한국산학기술학회논문지
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• 제12권1호
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• pp.545-551
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• 2011

최근 고품질의 수돗물에 대한 소비자의 요구가 상승함에 따라 상수도 배급수관의 내부 부식에 의한 수질악화 및 부식제어 연구에 대한 관심이 높아지고 있다. 이에 따라 노후 관 교체 사업을 대신하여 수질 관리를 위한 부식 제어 수단을 강구하지 않고서는 근본적인 문제 해결이 이루어질 수 없는 실정이다. 본 연구에서는 수질안정화 약품 주입에 의한 상수도관 내부 부식제어 효율을 평가하기 위해 Pilot Plant 실험을 실시하였으며, 부식성제어 효율은 물의 부식성을 나타내는 LSI(Langelier Saturation Index)값에 의해 평가되었다. 실험결과, Pilot Plant에 의해 제조된 반응수는 수질안정화 약품인 액상소석회($Ca(OH)_2$, liquid lime)의 주입으로 부식성이 개선되어 철 용출이 억제되는 효과가 확인되었다. 강관과 동관을 절단하여 제작한 시편의 부식도 측정을 통해 각각 35.4, 44.5%의 부식제어 효과가 있음을 확인하였고 수질안정화 약품이 주입된 Sample관이 더 두터운 부식 생성물 층을 갖고 있는 것으로 밝혀졌으며, 결과적으로 수질안정화 약품을 투입한 배관이 부식 방지 측면에서 안정한 수질을 갖고 있음을 알 수 있었다.

• ETRI Journal
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• 제31권3호
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• pp.345-347
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• 2009

This letter presents an alternative analytical expression for computing the probability of an M-ary phase shift keying (MPSK) wedge-shaped region in an additive white Gaussian noise channel. The expression is represented by the cumulative distribution function of known noncentral F-distribution. Computer simulation results demonstrate the validity of our analytical expression for the exact computation of the symbol error probability of an MPSK system with phase error.

• 한국통신학회:학술대회논문집
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• 한국통신학회 2004년도 하계종합학술발표회논문초록집
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• pp.393-393
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• 2004

• 한국시뮬레이션학회:학술대회논문집
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• 한국시뮬레이션학회 1999년도 추계학술대회 논문집
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• pp.272-277
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• 1999

The necessity of voice recording device was increased using voice signal IC with designed LSI/VLSI. The control unit which developed here voice recorder has low power dissipation, portable, and comfortable using voice source. However, the Korea voice recorder abilities far behind of foreign products for its performance and size on sailing. So we used Chua circuit to improvement voice quality abilities after minimize power supply device and circuit by designing voice recording device into lower power dissipation power circuit.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.789-792
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• 1993

We have proposed a fuzzy model for behavior of vehicles in the road traffic simulation system with microscopic model for analyzing traffic jam in the broad areas. It can exactly simulate each vehicle's behavior. We propose a new hardware processor to simulate fuzzy decision-making mechanism for its model. This paper describes the functions, performance and structure of the hardware processor.

• 대한전자공학회논문지
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• 제16권2호
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• pp.35-42
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• 1979

엘리베이터 시스템은 의치 및 속도제어를 동시에 요구하는 시tm템으로 하드웨어로 구성된 종래의 엘리베이터 시스템의 제어장치를 최근에 발달된 micro- computer의 도움으로 간단화 시킬 수 있는 가능성을 연구 보고하였다. 본 논문은 microprocessor를 이용한 controller hardware 의 구성과 본 hardware에 따른 제어방식을 설명하였고, 이 방식을 이용하여 본 시그템이 주어진 속도유선에 따라 동작하는 것을 실험을 통하여 보였다. 사용된 엘리베이터 모힌의 상태방정식을 사용한 제어프로그램을 적용하여 실험한 결과, 일반적 엘리베이터 시스템에 micro-computer가 사용될 수 있는 가능성이 있음을 보였다.

• Journal of Electrical Engineering and Technology
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• 제4권4호
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• pp.559-565
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• 2009

Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. The high switching activity of combinational circuits is an unnecessary operation in scan shift mode. In this paper, we present a novel architecture to reduce test power dissipation in combinational logic by blocking signal transitions at the logic inputs during scan shifting. We propose a unique architecture that uses dmuxed scan flip-flop (DSF) and transmission gate as an alternative to muxed scan flip-flop. The proposed method does not have problems with auto test pattern generation (ATPG) techniques such as test application time and computational complexity. Moreover, our elegant method improves performance degradation and large overhead in terms of area with blocking logic techniques. Experimental results on ITC99 benchmarks show that the proposed architecture can achieve an average improvement of 30.31% in switching activity compared to conventional scan methods. Additionally, the results of simulation with DSF indicate that the powerdelay product (PDP) and area overhead are improved by 28.9% and 15.6%, respectively, compared to existing blocking logic method.

• 센서학회지
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• 제30권2호
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• pp.114-118
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• 2021

In this study, the sensitivity of an active pixel sensor (APS) was adjusted by employing a gate/body-tied (GBT) p-channel metal-oxide semiconductor field-effect transistor (PMOSFET)-type photodetector with a transfer gate. A GBT PMOSFET-type photodetector can amplify the photocurrent generated by light. Consequently, APSs that incorporate GBT PMOSFET-type photodetectors are more sensitive than those APSs that are based on p-n junctions. In this study, a transfer gate was added to the conventional GBT PMOSFET-type photodetector. Such a photodetector can adjust the sensitivity of the APS by controlling the amount of charge transmitted from the drain to the floating diffusion node according to the voltage of the transfer gate. The results obtained from conducted simulations and measurements corroborate that, the sensitivity of an APS, which incorporates a GBT PMOSFET-type photodetector with a built-in transfer gate, can be adjusted according to the voltage of the transfer gate. Furthermore, the chip was fabricated by employing the standard 0.35 ㎛ complementary metal-oxide semiconductor (CMOS) technology, and the variable sensitivity of the APS was thereby experimentally verified.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권2호
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• pp.75-79
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• 2009

A system-on-a-chip communication architecture has a significant impact on the performance and power consumption of modern multi-processors system-on-chips (MPSoCs). However, customization of such architecture for a specific application requires the exploration of a large design space. Thus, system designers need tools to rapidly explore and evaluate communication architectures. In this paper we present the method for application-specific low-power bus architecture synthesis at system-level. Our paper has two contributions. First, we build a bus power model of AMBA AXI bus communication architecture. Second, we incorporate this power model into a low-power architecture exploration algorithm that enables system designers to rapidly explore the target bus architecture. The proposed exploration algorithm reduces power consumption by 20.1% compared to a maximally connected reduced matrix, and the area is also reduced by 20.2% compared to the maximally connected reduced matrix.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권4호
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• pp.249-254
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• 2005

This paper presents a system-on-a-chip (SOC) design for digital TV. The single LSI incorporates almost all essential parts such as CPU, ISO/IEC 11172/13818 system/audio/video decoders, a video post-processor, a graphics/OSD processor and a display processor. It has analog IP's inside such as video DACs, an audio PLL, and a system PLL to reduce the system-level implementation cost. Descramblers and Smart Card interface are included to support widely used conditional access systems. The video decoder can decode two video streams simultaneously. The DSP-based audio decoder can process various audio coding specifications. The functional blocks for video quality enhancement also form outstanding features of this SoC. The SoC supports world-wide major DTV services including ATSC, ARIB, DVB, and DIRECTV.