• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2313-2315
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• 2003

This paper presents the development methods which Samsung GPS baseband chip is called S3E4510X. Specification of S3E4510X and design methodology of baseband architecture is presented with a study of their effects. Also GPS core block and software are described in detail. We designed and implemented the test board with RF module for evaluating performance via static test dynamic test and each performance factors using live signal and CPS simulator. Test results show that our development GPS baseband chip have effectively performance for mobile handset Location Based Service (LBS) and its practical use for navigation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.229-236
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• 2005

This paper presents a system level architecture evaluation technique that leverages transaction level modeling but also significantly extends it to the realm of system level performance evaluation. A major issue lies with the modeling effort. To reduce the modeling effort the proposed technique develops the concept of worst case scenarios. Since the memory controller is often found to be an important component that critically affects the system performance and thus needs optimization, the paper further addresses how to evaluate and optimize the memory controllers, focusing on the test environment and the methodology. The paper also presents an industrial case study using a real state-of-the-art design. In the case study, it is reported that the proposed technique has helped successfully find the performance bottleneck and provide appropriate feedback on time.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.221-228
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• 2005

In this work, our goal is to develop a fast and accurate power model of the ARM926EJ-S processor in the industrial design environment. Compared with existing work on processor power modeling which focuses on the power states of processor core, our model mostly focuses on the cache power model. It gives more than 93% accuracy and 1600 times speedup compared with post-layout gate-level power estimation. We also address two practical issues in applying the processor power model to the real design environment. One is to incorporate the power model into an existing commercial instruction set simulator. The other is the re-characterization of power model parameters to cope with different gate-level netlists of the processor obtained from different design teams and different fabrication technology.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1305-1308
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• 1987

This paper presents a design of an optimized implantable biotelemetry system and the fabrication of custom CMOS LSI for implementing this system. The internal circuits of this system are fabricated on a single silicon chip with a size of $4{\times}5mm^2$. This LSI is designed and fabricated not only to get as small size and low power dissipation as possible, but also to have multiple function. Its main functions are to select one of implanted sensors and to accomplish ON - OFF power switching of an implanted battery by receiving appropriate Command signals and control signals fran external circuits. The internal system which was assembled on a bread-board using fabricated LSI chip is confirmed to work as designed. The total power dissipation of this interal system was $10.12{\mu}W$.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1559-1562
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• 2002

This paper describes a 0.13um ultra-high speed 1Mb CMOS SRAM macro with 1.7ns access time. It achieves ultra-high speed operation using two novel approaches. First, it uses process insensitive sense amplifier (Double-Equalized Sense Amplifier) which improves voltage offset by about 10 percent. Secondly, it uses new replica-based sense amplifier driver which improves bit- line evaluation time by about 10 percent compared to the conventional technique. The various memory macros can be generated automatically by using a compiler, word-bit size from 64kb to 1 Mb including repairable redundancy circuits.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.89-101
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• 2005

Research on highly abstracted system modeling and simulation has received a great deal of attention as of the concept of platform based design is becoming ubiquitous. From a practical design point of view, such modeling and simulation must consider the following: (i) fast simulation speed and cycle accuracy, (ii) early availability for early stage software development, (iii) inter-operability with external tools for software development, and (iv) reusability of the models. Unfortunately, however, all of the previous works only partially addresses the requirements, due to the inherent conflicts among the requirements. The objective of this study is to develop a new system design methodology to effectively address the requirements mentioned above. We propose a new transaction-level system modeling methodology, called ViP (Virtual Platform). We propose a two-step approach in the ViP method. In phase 1, we create a ViP for early stage software development (before RTL freeze). The ViP created in this step provides high speed simulation, lower cycle accuracy with only minor modeling effort.(satisfying (ii)). In phase 2, we refine the ViP to increase the cycle accuracy for system performance analysis and software optimization (satisfying (i)). We also propose a systematic ViP modeling flow and unified interface scheme based on utilities developed for maximizing reusability and productivity (satisfying (ii) and (iv)) and finally, we demonstrate VChannel, a generic scheme to provide a connection between the ViP and the host-resident application software (satisfying (iii)). ViP had been applied to several System-on-a-chip (SoC) designs including mobile applications, enabling engineers to improve performance while reducing the software development time by 30% compared to traditional methods.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.119-120
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• 2007

반도체 공정에서 사용되는 ILD막질 중 oxy-nitrde(SiON) film은 contact etch stopper, photo공정을 위한 ARL(anti-reflection lay떠 그리고, 후속공정의 plasma damage에 대한 blocking layer로서의 역할을 담당하며 많은 공정에 널리 사용되고 있다. 그러나 막질 자체의 불완전성 (trap site, dangling bond)에 의해 cell current instability(CCI) 특성을 악화 시킬 수 있어 이에 대한 원인규명 및 대책이 요구되었다. 본 연구는 미국 S사(社) super flash memory에서 oxy-nitride 막질 증착 시의 gas flow량에 따른 CCI 특성변화를 연구하고 최적의 공정조건을 제시하고자 한다.

• IE interfaces
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• v.16 no.3
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• pp.344-351
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• 2003

Critical dimension is one of the most important characteristics of up-to-date integrated circuit devices. Hence, critical dimension control in a semiconductor wafer fabrication process is inevitable in order to achieve optimum device yield as well as electrically specified functions. Currently, in complex semiconductor wafer fabrication processes, statistical methodologies such as Shewhart-type control charts become crucial tools for practitioners. Meanwhile, given a critical dimension sampling plan, the analysis of variance technique can be more effective to investigating critical dimension variation, especially for on-chip and on-wafer variation. In this paper, relating to a typical sampling plan, linear statistical models are presented for the analysis of critical dimension variation. A case study is illustrated regarding a semiconductor wafer fabrication process.

• Korean Journal of Materials Research
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• v.34 no.2
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• pp.111-115
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• 2024

Silicon carbide (SiC) has emerged as a promising material for next-generation power semiconductor materials, due to its high thermal conductivity and high critical electric field (~3 MV/cm) with a wide bandgap of 3.3 eV. This permits SiC devices to operate at lower on-resistance and higher breakdown voltage. However, to improve device performance, advanced research is still needed to reduce point defects in the SiC epitaxial layer. This work investigated the electrical characteristics and defect properties using DLTS analysis. Four deep level defects generated by the implantation process and during epitaxial layer growth were detected. Trap parameters such as energy level, capture-cross section, trap density were obtained from an Arrhenius plot. To investigate the impact of defects on the device, a 2D TCAD simulation was conducted using the same device structure, and the extracted defect parameters were added to confirm electrical characteristics. The degradation of device performance such as an increase in on-resistance by adding trap parameters was confirmed.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.2
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• pp.79-93
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• 1997

This paper presents a linear shift-invariant system euqivalent to morphological dilation for a memoryless uniform source in the sense of the power spectral density function, and comares it with dialtion. This equivalent LSI system is found through spectral decomposition and, for dilation and with windwo size L, it is shown to be a finite impulse response filter composed of L-1 delays, L multipliers and three adders. Th ecoefficients of the equivalent systems are tabulated. The comparisons of dilation and its equivalent LSI system show that probability density functions of the output sequences of the two systems are quite different. In particular, the probability density functon from dilation of an independent and identically distributed uniform source over the unit interval (0, 1) shows heavy probability in around 1, while that from the equivalent LSI system shows probability concentration around themean vlaue and symmetricity about it. This difference is due to the fact that dilation is a non-linear process while the equivalent system is linear and shift-ivariant. In the case that dikation is fabored over LSI filters in subjective perforance tests, one of the factors can be traced to this difference in the probability distribution.