• Proceedings of the KIPE Conference
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• 1996.06a
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• pp.109-112
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• 1996

In this paper, we composed utility interactive photovoltaic generation system of current source inverter, and controlled that low harmonic and high power factor are hold by supposing control and compensation method which is concerned with synchronous signal distortion and modulation delay. And we put parallel resonant circuit into dc link, so, magnitude of direct reactance was reduce by restraining direct current pulsation which had accumulation of pulsating power in alternating electrolytic condenser. Also we controlled that modulation factor is operated around maximum output of solar cell.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.51 no.3
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• pp.126-131
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• 2002

This paper is proposed to position and speed control of interior permanent magnet synchronous motor(IPMSM) drive without mechanical sensor. The rotor position, which is an essential component of any vector control schemes, is calculated through the instantaneous stator flux position and an estimated flux value of rotating reference frame. A closed-loop state observer is implemented to compute the speed feedback signal. The validity of the proposed sensorless scheme is confirmed by simulation and its dynamic performance is examined in detail.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.108-110
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• 2018

This paper proposes shortcircuit fault protection method in a synchronous buck converter using the PCB pattern Rogowski coil. The PCB pattern Rogowski coils are embedded in the gate driver to measure the device currents of the top and bottom side. When shortcircuit occurs in the system, the gate signal is blocked by the proposed fault protection method using the device current. The simulation and experimental results show that the proposed fault protection method is verified in the shortcircuit system.

• Proceedings of KOSOMES biannual meeting
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• 2006.11a
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• pp.181-186
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• 2006

Geostationary Orbit satellite, unlike other sun-synchronous polar-orbit satellites, will be able to take a picture of a large region several times a day (almost with everyone hour interval). For geostationary satellite, the target region is fixed though the location of sun is changed always. However, Sun-synchronous polar-orbit satellites able to take a picture of target region same time a everyday. Thus Ocean signal is almost same. Accordingly, the ocean signal of a given target point is largely dependent on time. In other words, the ocean signal detected by geostationary satellite sensor must translate to the signal of target when both sun and satellite are located in nadir, using another correction model. This correction is performed with a standardization of signal throughout relative geometric relationship among satellite-sun-target points. This relative ratio called bidirectional factor. To find relationship between time and $[L_w]_N$/Bidirectional Factor differences, we are calculate solar position, geometry parameters. And reflectance, total radiance at the top of atmosphere(). And water leaving radiance, normalized water leaving radiance. And calculate bidirectional factor, that is the ratio of $[L_w]_N$ between target region and aiming the point. Then, we can make the bidirectional factor lookup table for one year imaging. So, we suggested for necessary to simulation experiment bidirectional factor in more various condition(wavelength and ocean/air condition).

• Proceedings of the KIPE Conference
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• 1997.07a
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• pp.65-69
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• 1997

Generally, we often use a speed sensor based on a rotary encoder and we can obtain a speed information by counting the increased or decreased number of encoder pulses in a sampling period. However, these speed measurement systems do not inherently produce a true, instantaneous speed information and them the speed ripple is generated by speed measurement errors. In order to overcome this problem, speed observer is used for the accurate speed measurement and improvement of speed ripple for Permanent Magnet Synchronous Motor (PMSM) in this paper. Speed observer estimates the instantaneous speed at each sampling instant. This estimated speed signal is then used as the speed feedback signal for the speed loop control. The proposed speed observer system is proved simulation using SABER simulation S/W.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.524-526
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• 2011

This paper focuses on study on PWM converter control under unbalanced network condition. Voltage unbalance in a three-phase system causes the performance deterioration by producing 120 Hz voltage ripples in the DC link and 120 Hz ripple in reactive power. To eliminate the ripples, both positive and negative sequence currents should be controlled simultaneously. In this paper four PI controllers on synchronous reference frame is implemented to control D and Q currents in both positive and negative sequence. Positive and negative sequence signal extraction is done using delay signal cancellation method. Simulation results show satisfactory performance in suppressing 120 Hz ripples.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.534-537
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• 1998

In this paper, a set of novel self-timed latches are introduced and analyzed. These latches have no back-to-back connection as in conventional self-timed latch, and both inverting and noninerting outputs are evaluated simultaneously leading to thigher oepating frequencies. Power consumption of these latches ar ealso comparable to or less than that of conventional circuits. Novel type of cross-coupled inverter used in the proosed circuits implements static operatin without signal fighting with the main driver during signal transition. Proposed latches ar tested using a 0.6.mu.m triple-poly triple-metal n-well CMOS technology. The resutls indicates that proposed active-low sefl-timed latch (ALSTL) improves speed by 14-34% over conventional NAND SR latch, while in active-high self-timed latch (AHSTL) the improvements are 15-35% with less power as compared with corresponding NORA SR latch. These novel latches have been successfully implemented in a high-speed synchronous DRAM (SDRAM).

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.8
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• pp.1-9
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• 1992

Radio data system is a next-generation broadcasting system of digital information communication which multiplexes the digital data into the FM stereo signal in VHF/FM band and provides important and convenient service features. And radio data are composed of groups which are divided into 4 blocks with information word and check word. In this paper, radio data receiver is developed which recovers and process radio data to provide services. Then we confirm that 7dB SNR is required to be 10S0-5TBER of demodulation. Deconding process of shortened-cyclic-decoder has been simulated by computer. Also, the time-compression (by 16 times) method has been adopted for the RDS features post-processing. Via the error probability calculation, simulation and experimentation, the developed receiver system is proved to satisfy the system specification of EBU and implemented by general logic gates and analog circuits.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 1999.10a
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• pp.119-124
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• 1999

This paper presents new approach to technology pattern recognition of camera back cover and test of soldering. In real-time implementing of pattern recognition camera back cover and test of soldering, the MVB-03 vision board has been used. Image can be captured from standard CCD monochrome camera in resolutions up to 640$\times$480 pixels. Various options re available for color cameras, a synchronous camera reset, and linescan cameras. Image processing os performed using Texas Instruments TMS320C31 digital signal processors. Image display is via a standard composite video monitor and supports non-destructive color overlay. System processing is possible using c30 machine code. Application software can be written in Borland C++ or Visual C++

• Proceedings of the KIEE Conference
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• 1995.07b
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• pp.922-924
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• 1995

The modeling of accurate timing in storage elements of ASIC cell library was studied. The propagation delay time of clock signal affects the critical time and this can cause malfunction in the chip designed in synchronous. In this paper, an analysis on the effect of input slope of clock signal in timing modeling were carried out. For the first time, in ASIC design, the design guides that can be used in both $0.6{\mu}M$ and $0.8{\mu}m$ design rule were offered, reducing the run time of SPICE and the time of cell library development.