• Journal of Power Electronics
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• v.16 no.1
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• pp.18-26
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• 2016

This paper proposes a compensation algorithm for reducing a specific ripple component on synchronous reference frame phase locked loop (SRF-PLL) in grid-tied single-phase inverters. In general, SRF-PLL, which is based on all-pass filter to generate virtual voltage, is widely used to estimate the grid phase angle in a single-phase system. In reality, the estimated grid phase angle might be distorted because the phase difference between actual and virtual voltages is not 90 degrees. That is, the phase error is caused by the difference between cut-off frequency of all-pass filter and grid frequency under grid frequency variation. Therefore, the effects on phase angle and output current attributed to the phase error are mathematically analyzed in this paper. In addition, the proportional resonant (PR) controller is adapted to reduce the effects of phase error. The validity of the proposed algorithm is verified through several simulations and experiments.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.2
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• pp.92-98
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• 2019

Accurate estimation of motor parameters is required in some motor control applications. For example, the value of stator resistance is required for stator flux-oriented control mostly used in doubly fed induction generator systems. Stator resistance is not a constant value and continuously changes due to the rise in temperature during motor operation. Estimation errors degrade the control performance. Hence, this study proposes a simple stator resistance estimation method. In this scheme, the differential components of voltage and current values are used to eliminate the dead-time effect, and Kalman filter algorithm is applied to reduce the error according to measurement noise. Simulation and experimental results obtained with a permanent magnet motor show the validity of the proposed algorithm.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.12
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• pp.83-87
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• 2015

This paper presents a simple notch filter, which is so suitable for three-phase unbalanced and distorted power line. In the d-q synchronous transformation, three-phase unbalanced and distorted voltages generate lots of ripple voltages on d-q axes. The ripples make disturbances on controllers such as PLL of phase tracking. Unbalanced state makes ripple of double the frequency of power line. Odd harmonics 5th and 7th on the line make even 4th and 6th ripples on d-q axes due to the rotating reference frame, respectively. Cascaded two comb filters, delay lines 1/4T and 1/8T, are adopted for the ripple rejection. The filter rejects harmonics 2nd, 4th, 6th, 10th and so on. They are very effective to remove the ripples of both unbalance and distortion. The filter, implemented by two FIFOs on an experimental system, is adopted on a PLL controller of power line phase tracking. Through the simulation and experimental results, performance of the proposed comb filter has been validated.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.4
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• pp.624-632
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• 1994

In this paper, we implement modulator of 155Mbps 64QAM RF MODEM, CCITT G. 707 SDH(Synchronous Digital Hierachy) 1 level, for DMR(DIgital Microwave Radio) STM-1 transmission, PSF(Pulse Shaping Filter) plays an important role to analyze modulator. We use 7 orders elliptic filter instead of Chebychev filter(roll-off facter a=0.5)in this paper. we obtain that roll-off factor, a is 0.33, group delay is less than 10nsec using this filter. Also we get -20dBm output level after passing the PSF, and 0dBm output level after passing the IF amplifier.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.4
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• pp.329-332
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• 2020

A back-electromotive force (back-EMF) estimator for a permanent magnet synchronous motor (PMSM) uses the three-phase voltage references of a current controller to estimate rotor position. However, owing to voltage drops caused by the nonlinear characteristics of switches and passive components, the actual voltage in the motor and the three-phase voltage reference may not match. This study proposes a sensorless control method using a sine-wave output filter applied between the motor drive system and PMSM. The precise voltage in the motor can be measured with the sine-wave output filter and applied to the input of the estimator. Moreover, given that the voltage in the motor can be measured precisely at extremely low speeds, the stable operation range of the back-EMF estimator can be secured. Experimental results show that the proposed sensorless control method has stable operation at extremely low speeds compared with conventional sensorless control.

• Journal of Fisheries and Marine Sciences Education
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• v.29 no.3
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• pp.778-784
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• 2017

This paper proposes a sensorless speed control of a permanent magnet synchronous motor (PMSM) based on an adaptive sliding mode observer (SMO) for electric propulsion system of small ships. An adaptive observer gain is proposed based on the Lyapunov's stability criterion to reduce the chattering problem at any speed operation instead of the constant gain observer. Furthermore, a cascade low-pass filter with variable cut-off frequency is suggested to strengthen the filtering capability of the observer. The experimental results from a 1.5 kW PMSM drive are provided to verify the effectiveness of the proposed adaptive SMO. The result shows that the proposed method gives good speed control performances even when the PMSM operates at 0.5% from its rated speed value.

• Journal of Power System Engineering
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• v.18 no.5
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• pp.129-136
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• 2014

This paper proposes improvement on sensorless vector control performance of a permanent magnet synchronous motor (PMSM) with sliding mode observer. An adaptive observer gain and second order cascade low-pass filter (LPF) were used to improve the estimation accuracy of the rotor position and speed. The adaptive observer gain was applied to suppress the chattering intensity and obtained by using the Lyapunov's stability criterion. The second order cascade LPF was designed for the system to escalate the filtering performance of the back-emf estimation. Furthermore, genetic algorithm was used to optimize the system PI controller's performance. Simulation results showed the effectiveness of the suggested improvement strategy. Moreover, the strategy was useful for the sensorless vector control of PMSM to operate on the low-speed area.

• Journal of Power Electronics
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• v.17 no.6
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• pp.1553-1562
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• 2017

For the purpose of enhancing the performance of the shunt active power filter (APF), this paper presents a novel Fast Weighted Compound Control (FWCC) strategy based on the synchronous frame. In this control strategy, the proposed new repetitive controller can work faster and more stably by reducing the internal model cycle and introducing a damping coefficient. In addition, the harmonic detector can be removed to simplify the structure of the APF owing to the improvements. Furthermore, a proportional-integral (PI) controller is added to work in parallel with the repetitive controller by using a weighted ratio. Then, a convergence speed analysis and design algorithm are given in detail. Simulation and experimental results show that the harmonic distortion is reduced from 2.91% to 1.89%. In addition, the content for each of the characteristic harmonic orders has decreased by more than three times.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.11
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• pp.2081-2093
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• 1994

In this study, we design and implement 64 QAM demodulator which has 155 Mbps, first level of CCITT G707 SDH(Synchronous Digital Hierachy) for STM 1 signal transmission. Carrier recovery which effects the demodulator performance uses decision feedback carrier using 8 bits A/D converter. Also, PSF(Pulse Shaping Filter) is 7 order elliptic filter. Carrier recovery circuit is designed and implemented digital type which use high 3 bits of 8 bits conversion data as data and the order low bits as error data and hybrid type which use VCO and analog integrator. Therefore we obtain stable performance recovery.