• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.6
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• pp.992-997
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• 1987

This paper describes the design and fabrication of an integrated circuit that can separate the horizontal SYNC., vertical SYNC. and composite SYNC. signal included in a composite video signal. The circuit that is based on the comparator level samplign method can separate a stable SYNC. signal even from an external circuit with large variation. It has been fabrivated by the SST bipolar process. Its chip size is 1.5x1.5mm\ulcorner As a result, we succeeded in fabrication of IC which satisfied DC characteristics and SYNC. singal separator function.

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.6
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• pp.52-65
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• 1978

Computer-aided design of color TV circuits has been tried using circuit analysis programs. Due to the complexity of colorplexed composite video signals of the color TV, conventional methods are difficult to apply in the color TV circuit design. This paper describes how to design Y video circuit, chroma cicruit, AGC circuit, and sync separator circuit of color TV using analysis programs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.3
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• pp.247-259
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• 1992

In this paper, the types of the data exchange between a cell site and a cobile phonefor the call processing on the AMPS(Advanced Mobile Phone Service) are investigated, and the circuit for processing the wideband data stream according to the data types is designed and implemented. The circuit for detecting the Busy / Idle bit which is needed for determining the channel access, the circuit for detecting the word sync and the circuit for transmitting and receiving the wideband data is designed. The 3-out-of-5 majority vote of the 5received data is performed to reduce error and an algorithm requiring a small buffer size for real time processing of voting process is proposed. The method to overcome the computational complexity and the real time constraint of the conventional BCH decoding is proposed.

• Journal of Advanced Navigation Technology
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• v.11 no.2
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• pp.163-169
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• 2007

In this paper, we propose a method of trigger pulse generation to capture the image on time by making a synchronization between the x-ray generator and digital x-ray image acquisition system. we designed a wireless trigger pulse generation circuit to make a synchronization between x-ray generator and digital image acquisition system and analysis its performance. When it starts to detect a certain level of x-ray radiation or above from the air, this method starts to generate a ACQ_START signal to indicate the timing for image acquisition starting from digital image acquisition system. Hence, when it starts to detect under certain level of x-ray signal from the air, this method starts to generate a ACC_END signal to indicate the timing for image acquisition stop from digital image acquisition system. Image acquisition is activated only this time between ACQ_START and ACQ_END signal. By doing this wireless detecting of x-ray signal from remote, we can get more accurate timing for capturing the x-ray image and any type of x-ray generator can be connected to digital image acquisition system, regards of wired protocol. This makes easy installation. We could get 3.5 line pair / mm resolution at 20 mAs of x-ray level with resolution chart. This is same or better image comparing to conventional wired result.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.81-88
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• 2004

In this paper, we designed the outer encoder/decoder for the terrestrial DMB that is an advanced digital broadcasting standard, implemented, and verified by using ALTERA FPGA. In the encoder part, it was created the parity bytes (16 bytes) from the input packet (188by1e) of MPEG-2 TS and the encoded data was distributed output by the convolutional interleaver for Preventing burst errors. In the decoder part, It was proposed the algorithm that detects synchronous character suitable to DMB in transmitted data from the encoder. The circuit complexity in RS decoder was reduced by applying a modified Euclid's algorithm. This system has a capability to correct error of the maximum 8 bytes in a packet. After the outer encoder/decoder algorithm was verified by using C language, described in VHDL and implemented in the ALTERA FPGA chips.