• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.1
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• pp.69-77
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• 1989

A hologram scanner for POS bar code symb9ol readers has been developed. This system is composed of scanning optics, optical detector, video signal circuitary and preprocessor. In contrast to conventional scanners using polygonal mirrors, which complicate the scanning optics, the hologram scanner developed in this research was made up with simple optics and higher reading performance was achieved. And in order to read abar code symbol omnidirectionally with highdensity scan patterns, the new real time decoding technique was proposed. The advantage of this technique is less hardware and lower clock rate. High speed processing and improved readability for tilted symbol was confirmed experimentally.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.12
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• pp.103-110
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• 2005

The performance of maximum likelihood(ML) detection for the given channel is analyzed in spatially multiplexed MIMO system. In order to obtain the vector symbol error rate, we define error vectors which represent the geometrical relation between lattice points. The properties of error vectors are analyzed to show that all lattice points in infinite lattice almost surely have four nearest neighbors after random channel transformation. Using this information and minimum distance obtained by the modified sphere decoding algorithm, we formulate the analytical performance of vector symbol error over the given channel. To verify the result, we simulate ML performance over various random channel which are classified into three categories: unitary channel, dense channel, and sparse channel. From the simulation results, it is verified that the derived analytical result gives a good approximation about the performance of ML detector over the all random MIMO channels.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.87-95
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• 2014

This paper describes a dual channel receiver design for CIS interfaces. Each channel includes CTLE(Continuous Time Linear Equalizer), sampler, deserializer and clocking circuit. The clocking circuit is composed of PLL, PI and CDR. Fast lock acquisition time, short latency and better jitter tolerance are achieved by adding OSPD(Over Sampling Phase Detector) and FSM(Finite State Machine) to PI-based CDR. The CTLE removes ISI caused by channel with -6 dB attenuation and the lock acquisition time of the CDR is below 1 baud period in frequency offset under 8000ppm. The voltage margin is 368 mV and the timing margin is 0.93 UI in eye diagram using 65 nm CMOS technology.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.6
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• pp.10-14
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• 2015

In holographic data storage systems, data is recorded and read by page on a volume of storage medium, and it can increase transmission rate and storage capacity because of two-dimensional page-oriented data processing by charge-coupled devices. However, HDS suffers two-dimensional intersymbol interference unlike conventional data storages. In this paper, we propose a preprocessing method of decreasing ISI before read data in HDS pass to detector. This method has some advantage when we collaborate with the preprocessing for reducing misalignment error and modulation code.

• ETRI Journal
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• v.33 no.5
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• pp.661-669
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• 2011

In this paper, we propose an efficient soft-output signal detection method for spatially multiplexed multiple-input multiple-output (MIMO) systems. The proposed method is based on the ordered successive interference cancellation (OSIC) algorithm, but it significantly improves the performance of the original OSIC algorithm by solving the error propagation problem. The proposed method combines this enhanced OSIC algorithm with a multiple-channel-ordering technique in a very efficient way. As a result, the log likelihood ratio values can be computed by using a very small set of candidate symbol vectors. The proposed method has been synthesized with a 0.13-${\mu}m$ CMOS technology for a $4{\times}4$ 16-QAM MIMO system. The simulation and implementation results show that the proposed detector provides a very good solution in terms of performance and hardware complexity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.11
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• pp.1364-1373
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• 2016

Ultra High Definition Television (UHDTV) has attracted much attention as one of next generation broadcasting services. For the commercialization of UHD broadcasting service, standardization groups including the DVB (Digital Video Broadcasting) and the ATSC (Advanced Television Systems Committee) have decided to adopt the Orthogonal Frequency Division Multiplexing (OFDM) for signal transmission. However, when the carrier frequency is not properly synchronized at the receiver, inter-symbol interference (ISI) and inter-carrier interference (ICI) may occur. In order to avoid performance degradation resulting from ISI or ICI, receivers should synchronize the carrier frequency by using preambles and pilot symbols. However, there only few published literature dealing with the frequency offset estimation methods regarding the next generation terrestrial broadcasting. In this respect, this paper proposes a method to estimate timing and fractional frequency offset for the ATSC 3.0 system by using a preamble bootstrap symbol. The proposed detector can detect the fractional frequency offset by adding a complex conjugate product on the conventional estimator where only timing offset can be estimated.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.12C
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• pp.1044-1051
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• 2010

In this paper, we propose an efficient soft-output signal detection method for spatially multiplexed multiple input multiple output (MIMO) systems. The proposed method is based on the ordered successive interference cancellation (OSIC) algorithm, but it significantly improves the performance of the original OSIC algorithm by solving the error propagation problem. The proposed method combines this enhanced OSIC (ESIC) algorithm with a multiple ordering technique in a very efficient way. As a result, the log likelihood ratio (LLR) values can be computed by using a very small set of candidate symbol vectors. The proposed method has been implemented with a $0.13{\mu}m$ CMOS technology for a $4{\times}4$ 16-QAM MIMO system. The simulation and implementation results show that the proposed detector provides a very good solution in terms of performance and hardware complexity.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.8
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• pp.14-25
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• 2002

In this paper, we propose a modified AFC algorithm which is suitable for the implementation of WCDMA reverse link receiver modem. To reduce the complexity, the modified CP-FDD algorithm named 'Normalized CP-FDD' is applied to the AFC loop. The proposed FDD algorithm overcomes the conventional CP-FDD's sensitivity to the variance of input signal amplitude and increases the linear range of S -curve. Therefore, offset frequency estimation using the proposed scheme can be more stable than the conventional method. Unlike IS-95, since pilot symbol in WCDMA is not transmitted continuously, we introduce a moving average filter at the FDD input to increase the number of cross-product. So, tracking speed and stability are improved. For more rapid frequency acquisition and tracking, we adopt a multi-stage tracking mode. Using NCO having ROM table structure, the frequency offset is compensated. We applied the proposed algorithm in the implementation of WCDMA base station modem successfully.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.9
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• pp.668-676
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• 2018

In satellite communications, a modulation technique with a low peak-to-average power ratio, high transmission efficiency, and low bit error rate(BER) is required, and differential amplitude and phase shift keying(DAPSK) modulation technique has been appraised as a technology that meets these requirements. However, because conventional DAPSK modulation uses a regular constellation diagram, the Euclidean distance between the symbols in the inner concentric circles of the constellation are quite short. Such a characteristic degrades the BER. In this paper, we propose a DAPSK system that uses an efficient constellation assignment to improve the performance of existing DAPSK systems and evaluate the performance of the proposed scheme. From the simulation results, we confirm that the proposed 16-DAPSK system achieves an signal-to-noise ratio gain of 0.8 dB over the conventional approach at a BER condition of $10^{-4}$ when the number of symbols used in the symbol detector of the receiver is 2.

• Journal of Korea Multimedia Society
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• v.12 no.3
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• pp.329-334
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• 2009

When an optical disc is being played. the pick-up converts light to analog signal at first. The analog signal is equalized for removing the inter-symbol interference and then the equalized analog signal is converted into the digital signal for extracting the synchronized data and clock signals. There are a lot of algorithms that minimize the BER in extracting the synchronized data and clock when high. density optical disc like BD is being played in low speed. But if the high-density optical disc is played in high speed, it is difficult to adopt the same extraction algorithm to data PLL and PRML architecture used in low speed application. It is because the signal with more than 800MHz should be processed in those architectures. Generally, in the 0.13-${\mu}m$ CMOS technology, it is necessary to have the high speed analog cores and lots of efforts to layout. In this paper, the parallel data PLL and PRML architecture, which enable to process in BD 8x speed of the maximum speed of the high-density optical disc as the extracting data and clock circuit, is proposed. Test results show that the proposed architecture is well operated without processing error at BD 8x speed.