• Journal of the Korea Institute of Information and Communication Engineering
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• 제14권8호
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• pp.1868-1876
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• 2010

In this paper, we design a 256-bit EEPROM IP using only logic process-based devices. We propose EEPROM core circuits, a control gate (CG) and a tunnel gate (TG) driving circuit, to limit the voltages between the devices within 5.5V; and we propose DC-DC converters : VPP (=+4.75V), VNN (-4.75V), and VNNL (=VNN/3) generation circuit. In addition, we propose switching powers, CG_HV, CG_LV, TG_HV, TG_LV, VNNL_CG, VNNL_TG switching circuit, to be supplied for the CG and TG driving circuit. Simulation results under the typical simulation condition show that the power consumptions in the read, erase, and program mode are $12.86{\mu}W$, $22.52{\mu}W$, and $22.58{\mu}W$ respectively. Furthermore, the manufactured test chip operated normally and generated its target voltages of VPP, VNN, and VNNL as 4.69V, -4.74V, and -1.89V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제45권7호
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• pp.44-51
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• 2008

A stereo audio digital-to-analog converter (DAC) with a power amplifier using asymmetric pulse-width modulation (PWM) is presented. To adopt class-D amplifier mainly used in high-power audio appliances for head-phones application, this work analyzes the noise caused by the inter-channel interference during the integration and optimizes the design of the sigma-delta modulator to decrease the performance degradation caused by the noise. The asymmetric PWM is implemented to reduce switching noise and power loss generated from the power amplifier. This proposed architecture is fabricated in 0.13-mm CMOS technology. The proposed audio DAC including the power amplifier with single-ended output achieves a dynamic range (DR) of 95-dB dissipating 4.4-mW.

• Journal of Software Assessment and Valuation
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• 제16권2호
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• pp.109-115
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• 2020

In this paper, the problem that occurs when negative voltage is generated using an inexpensive buck device in an IT device that is supplied with a single power by an adapter or battery is analyzed. For the cause analysis, the principle of operation of the buck device and the principle of the inverter circuit were examined, and the circuit characteristics of the inverter circuit were analyzed using the buck device. As a result of the analysis, it was confirmed that the inverter circuit using the buck device initially needs a large starting current, and in particular, in the case of a current capacity that is less than the starting current in the circuit that supplies power, it was confirmed that it could fall into a state similar to the latch-up phenomenon. In order to confirm the analysis result, an experimental circuit was constructed and the input current was checked. If the supply current is sufficient, it is confirmed that over-current flows and starts. If the supply current is insufficient, the circuit cannot start and a latch-up phenomenon occurs.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• 제25권5호
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• pp.504-514
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• 2014

An MMIC multi-function chip with a low DC power consumption for an X-band active phased array radar system has been designed and fabricated using a 0.5 ${\mu}m$ GaAs p-HEMT commercial process. The multi-function chip provides several functions: 6-bit phase shifting, 6-bit attenuation, transmit/receive switching, and signal amplification. The fabricated multi-function chip with a compact size of $16mm^2(4mm{\times}4mm)$ exhibits a gain of 10 dB and a P1dB of 14 dBm from 7 GHz to 11 GHz with a DC low power consumption of only 0.6 W. The RMS(Root Mean Square) errors for the 64 states of the 6-bit phase shift and attenuation were measured to $3^{\circ}$ and 0.6 dB, respectively over the frequency.

• Proceedings of the KIEE Conference
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• 대한전기학회 2001년도 추계학술대회 논문집 전력기술부문
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• pp.216-218
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• 2001

The transformer role is very important in power system operation and control; also its price is very expensive. Therefore many kinds of the efforts for transformer protection have been executed. So for as, current differential relay(87) has been mainly used for transformer protection. But current differential relaying method has several troubles as followings. Differential current can be occurred by transformers inrush current between winding1 and winding2 of transformer when transformer is initially energized. Also harmonic restrained element used in current differential relaying method is one of the causes of relays mal-operation because recently harmonics in power system gradually increase by power switching devices(SVC, FACTS, DSC, etc). Therefore many kinds of effort have been executed to solve the trouble of current differential relay and one of them is method using ratio of increment of flux linkages(RIFL) of the primary and secondary windings. This paper introduces a novel protective relay for power transformers using RIFL of the primary and secondary windings. Novel protective relay successfully discriminates between transformer internal faults and normal operation conditions including inrush and this paper includes real time test results using RTDS(Real Time Digital Simulator) for novel protective relay. A novel protective relay was designed using the TMS320C32 digital signal processor and consisted of DSP module. A/D converter module, DI/DO module, MMI interface module and LCD display module and developed by Xelpower co., Ltd.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제45권12호
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• pp.65-72
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• 2008

This paper proposes a new dual-loop digital PLL(DPLL) using seamless frequency tracking methods. The dual-loop construction, which is composed of the coarse and fine loop for fast locking time and a switching noise suppression, is used successive approximation register technique and TDC. The proposed DPLL in order to compensate the quality of jitter which follows long-term of input frequency is newly added cord conversion frequency tracking method. Also, this DPLL has VCO circuitry consisting of digitally controlled V-I converter and current-control oscillator (CCO) for robust jitter characteristics and wide lock range. The chip is fabricated with Dongbu HiTek $0.18-{\mu}m$ CMOS technology. Its operation range has the wide operation range of 0.4-2GHz and the area of $0.18mm^2$. It shows the peak-to-peak period jitter of 2 psec under no power noise and the power dissipation of 18mW at 2GHz through HSPICE simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제40권11호
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• pp.83-94
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• 2003

In this paper. a highly linear and low glitch CMOS current mode digital-to-analog converter (DAC) by self calibration bias circuit is proposed. The architecture of the DAC is based on a current steering 6＋4 segmented type and new switching scheme for the current cell matrix, which reduced non-linearity error and graded error. In order to achieve a high performance DAC . novel current cell with a low spurious deglitching circuit and a new inverse thermometer decoder are proposed. The prototype DAC was implemented in a 0.35${\mu}{\textrm}{m}$ n-well CMOS technology. Experimental result show that SFDR is 60 ㏈ when sampling frequency is 32MHz and DAC output frequency is 7.92MHz. The DAC dissipates 46 mW at a 3.3 Volt single power supply and occupies a chip area of 1350${\mu}{\textrm}{m}$ ${\times}$750${\mu}{\textrm}{m}$.

• Journal of Advanced Navigation Technology
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• 제18권5호
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• pp.483-489
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• 2014

Proposed electronic ballast circuit for harmonic reduction includes adding lossless snubber circuit to DC-DC converter. To get inverter for changing DC-AC, a lamp has been changed to equivalence resistance in the standard lamp voltage and current data, also inverter circuit has been interpreted by being changed to R, L, C equivalence circuit. Using converted equivalent circuit, the most suitable circuit constant which can satisfy the characteristics of fluorescent lamps has been decided on and finally designed. It could not only eliminate distortion waveform from pulsation frequency in inverter direct side current but also reduce considerably pulsation rate and switching loss by making input current of inverter discontinuous. The validity for the results of this study has been verified through the experiment to measure harmonic occurrence after applying a newly-manufactured product of electronic ballast to 40 W line tube style fluorescent lamps.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제46권12호
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• pp.58-65
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• 2009

In this paper, we designed high voltage gate drive IC including dead time circuit in which capacitors controlled rising time and falling time, and schimitt-triggers controlled switching voltage. Designed High voltage gate drive IC improves an efficiency of half-bridge converter by decreasing dead time variation against temperature and has variable dead time by the capacitor value. and its power dissipation, which is generated on high side part level shifter, has decreased 52 percent by short pulse generation circuit, and UVLO circuit is designed to prevent false-operation. We simulated by using Spectre of Cadence to verify the proposed circuit and fabricated in a 1.0um process.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• 제16권2호
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• pp.151-155
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• 2016

In this paper, we present the LED dimming control system by using ADPCM (Adaptive Differential Pulse Code Modulation). This ADPCM apparatus accurately controls the LED current with high resolution reducing the RFI (radio frequency interference) due to the spreading out of the harmonics of current of pulses. Additionally, this makes it easier to increase the accuracy of control operation. This study introduces to make a digitally controlled circuit for controlling LED with high-energy efficient by adopting pulse current to LED. The LED current drive system we designed are two systems, the digitally-controlled unit and analog switching mode power supply unit, can be developed separately. The simulation shows the sigma delta modulation of digital to analog converter's output when the input level is 0.7. From this simulation, the output is approached to accurately 0.15% to target value with 510 pulses.