• IMMUNE NETWORK
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• v.4 no.4
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• pp.216-223
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• 2004

Background: It is well known that IgA isotype switching is induced by $TGF-{\beta}1$. LPS-activated mouse normal B cells well differentiate into IgA secreting plasma cells under the influence of $TGF-{\beta}1$. Nevertheless, there are lots of difficulties in studying normal B cells in detail because it is not simple to obtain highly purified B cells, showing low reproducibility and transfection efficacy, moreover impossible to keep continuous culture. To overcome these obstacles, it is desperately needed to develop B cell line which acts like normal B cells. In the present study, we investigated whether CH12F3-2A lymphoma cells are appropriate for studying IgA isotype switching event. Methods: CH12F3-2A B cell line was treated with LPS and $TGF-{\beta}1$, then levels of germ-line (GL) transcripts were measured by RT-PCR, and $GL{\alpha}$ promoter activity was measured by luciferase assay. In addition, membrane IgA (mIgA) expression and IgA secretion were determined by FACS and ELISA, respectively. Results: $TGF-{\beta}1$, regardless of the presence of LPS, increased level of $GL{\alpha}$ transcripts but not $GL{\gamma}2b$ transcripts. However, IgA secretion was increased dramatically by co-stimulation of LPS and $TGF-{\beta}1$. Both mIgA and IgA secretion in the presence of $TGF-{\beta}1$ were further increased by over-expression of Smad3/4. Finally, $GL{\alpha}$ promoter activity was increased by $TGF-{\beta}1$. Conclusion: CH12F3-2A cell line acts quite similarly to the normal B cells which have been previously reported regarding IgA expression. Thus, CH12F3-2A lymphoma cell line appears to be adequate for the investigation of the mechanism(s) of IgA isotype switching at the cellular and molecular levels.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.640-648
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• 2014

Excessive power dissipation is one of the major issues in the testing of VLSI systems. Many techniques are proposed for scan test, but there are not so many for logic BIST because of its unmanageable randomness. This paper presents a novel low switching activity BIST scheme that reduces toggle frequency in the majority of scan chain inputs while allowing a small portion of scan chains to receive pseudorandom test data. Reducing toggle frequency in the scan chain inputs can reduce test power but may result in fault coverage loss. Allowing a small portion of scan chains to receive pseudorandom test data can make better uniform distribution of 0 and 1 and improve test effectiveness significantly. When compared with existing methods, experimental results on larger benchmark circuits of ISCAS'89 show that the proposed strategy can not only reduce significantly switching activity in circuits under test but also achieve high fault coverage.

• The KIPS Transactions:PartA
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• v.12A no.1 s.91
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• pp.1-6
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• 2005

This paper presents a new algorithm on low power survivor path memory implementation of the trace-back systolic array Viterbi algorithm. A novel idea is to reuse the already-generated trace-back routes to reduce the number of trace-back operations. And the spurious switching activity of the trace-back unit is reduced by making use of a clock gating method. Using the SYNOPSYS power estimation tool, DesignPower, our experimental result shows the average $40{\%}$ power reduction and $23{\%}$ area increase against the trace-back unit introduced in [1].

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.17-29
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• 1999

This paper presents a high level synthesis method targeting low power consumption for data-dominated CMOS circuits (e.g., DSP). The high level synthesis is divided into three basic tasks: scheduling, resource and register allocation. For lower power scheduling, we increase the possibility of reusing an input operand of functional units. For a scheduled data flow graph, a compatibility graph for register and resource allocation is formed, and then a special weighted network is then constructed from the compatibility graph and the minimum cost flow algorithm is performed on the network to obtain the minimum power consumption data path assignment. The formulated problem is then solved optimally in polynomial time. This method reduces both the switching activity and the capacitance in synthesized data path. Experimental results show 15% power reduction in benchmark circuits.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.9-16
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• 2004

The state assignment for a finite state machine greatly affects the delay, area, power dissipation, and testabilities of the sequential circuits. In order to improve the testabilities and power consumption, a new state assignment technique based on m-block partition is introduced in this paper. The algorithm minimizes the dependencies between groups of state variables are minimized and reduces switching activity by grouping the states depending on the state transition probability. In the sequel the length and number of feedback cycles are reduced with minimal switching activity on the state variables. Experiment shows significant improvement in testabilities and Power dissipation for benchmark circuits.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.6
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• pp.628-634
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• 2000

We propose a data coding scheme for reducing' power consumption and ElVII in transmitting a sequence of data from LCD controller to LCD driver. The proposed coding scheme makes use of reducing data transitions in general text image of PC. It can be implemented with a little hardware and applied to the real-time applications of LCD driving system. We have executed computer simulations of the proposed coding scheme and compared the results of the proposed scheme with those produced by the existing coding schemes. The proposed coding scheme, compared to the existing ones, reduces the switching activity significantly in both of text and picture images.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.1
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• pp.81-90
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• 2004

The state assignment for a finite state machine greatly affects the delay, area, power dissipation, and testabilities of the sequential circuits. In order to improve the testabilities and power consumption, a new state assignment technique . based on m-block partition is introduced in this paper. By the m-block partition algorithm, the dependencies among groups of state variables are minimized and switching activity is further reduced by assigning the codes of the states in the same group considering the state transition probability among the states. In the sequel the length and number of feedback cycles are reduced with minimal switching activity on state variables. It is inherently contradictory problem to optimize the testability and power consumption simultaneously, however our new state assignment technique is able to achieve high fault coverage with less number of scan nfp flops by reducing the number of feedback cycles while the power consumption is kept low upon the low switching activities among state variables. Experiment shows drastic improvement in testabilities and power dissipation for benchmark circuits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.11A
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• pp.1092-1097
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• 2005

In this paper, we propose a low-power Booth multiplication which reduces the switching activities of partial products during multiplication process. Radix-4 Booth algorithm has a characteristic that produces the Booth encoded products with zero when input data have sequentially equal values (0 or 1). Therefore, partial products have higher chances of being zero when an input with a smaller effective dynamic range of two multiplication inputs is used as a multiplier data instead of a multiplicand. The proposed multiplier divides a multiplication expression into several multiplication expressions with smaller bits than those of an original input data, and each multiplication is computed independently for the Booth encoding. Finally, the results of each multiplication are added. This means that the proposed multiplier has a higher chance to have zero encoded products so that we can implement a low power multiplier with the smaller switching activity. Implementation results show the proposed multiplier can save maximally about $20\%$ power dissipation than a previous Booth multiplier.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.12C
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• pp.1256-1261
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• 2005

In this paper, we propose a low-power Booth multiplication which reduces the switching activities of partial products during multiplication process. Radix-4 Booth algorithm has a characteristic that produces the Booth encoded products with zero when input data have sequentially equal values (0 or 1). Therefore, partial products have higher chances of being zero when an input with a smaller effective dynamic range of two multiplication inputs is used as a multiplier data instead of a multiplicand. The proposed multiplier divides a multiplication expression into several multiplication expressions with smaller bits than those of an original input data, and each multiplication is computed independently for the Booth encoding. Finally, the results of each multiplication are added. This means that the proposed multiplier has a higher chance to have zero encoded products so that we can implement a low power multiplier with the smaller switching activity. Implementation results show the proposed multiplier can save maximally about $20\%$ power dissipation than a previous Booth multiplier.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.57-64
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• 2004

In this paper, we propose a RZ/HRZ mixture data transmission method for the asynchronous circuit design to reduce Power consumption. The dual-rail data with Rf decoding scheme is used to design asynchronous circuit, and it is easy to get a completion signal of the data validity from the native data as contrasted with sin91e-rail. However, the dual-rail scheme suffers from large chip area and increasing of Power consumption from all signals by the switching of the return-to-zero. We need to diminish number of circuit switching. The proposed RZ/HRZ data transmission reduces a switching activity to about 50% and it shows 23% lower power consumption than the conventional dual-rail coding with RZ's.