• Journal of Magnetics
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• v.17 no.1
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• pp.42-45
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• 2012

We have developed an alternating magnetic field stimulation system consisting of a switched-mode power supply and a digital control circuit which modulates a duty ratio to maintain a magnetic field intensity of a few mT even while the frequency increases up to 4 kHz with a controllable coil temperature below $30^{\circ}C$ in air. This duty ratio modulation and water circulation are advantageous for cell culture under ac-magnetic field stimulation by preventing the incubator from exceeding a cell-viable temperature of $37^{\circ}C$. Although the temperature of the coil when subjected to a sinusoidal voltage rapidly increased, that of our system modulated by the duty factor did not change. This is a potentially valuable method to investigate the effects of intermediate frequency magnetic field stimulation on biological entities such as cells, tissues and organs.

• Korean Journal of Optics and Photonics
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• v.19 no.3
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• pp.242-245
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• 2008

A four-channel selective microwave filter was demonstrated incorporating an optical resonator router, which is constructed by integrating a $1{\times}4$ space switch with an arrayed ring filters featuring different free spectral ranges. The center frequency of each channel was determined by the FSR of the corresponding ring resonator, and the four channels centered at 10 GHz, 16 GHz, 18 GHz and 20 GHz were individually selected to provide a bandpass filtering via the control voltage applied to the switched resonator.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.3
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• pp.19-25
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• 2008

In this paper, author proposes a novel step-up AC-DC chopper operated with power factor correction(PFC) and with high efficiency. The proposed chopper behaves with discontinuous current control(DCC) of input current. The input current waveform in the proposed chopper is got to be a discontinuous sinusoid form in proportion to magnitude of ac input voltage under the constant duty cycle switching. Therefore, the input power factor is nearly unity and the control method is simple. In the general DCC chopper, the switching devices are turned-on with the zero current switching, but turn-off of the switching devices is switched at current maximum value. To achieve a soft switching of the switching rum-off, the proposed chopper is used a new partial resonant circuit. The result is that the switching loss is very low and the efficiency of chopper is high.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.11
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• pp.730-734
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• 1999

In this study, it is the purpose to develope a cheap and compact repetitively pulsed $CO_2$ laser with pulse repetition rate range of 180 Hz. We used a SCR switched power supply as a high voltage pulsed supply, which is cheap and simple comparing to others. PIC one-chip microprocessor was used for precise control of a laser power supply on the control part. And the laser cavity was fabricated as an axial and water cooled type. The laser performance characteristics as various parameters, such as pulse repetition rate and gas pressure have been investigated. The experiment was done under the condition of total pressure of $CO_2, N_2$ and He from 4 Torr to 16 Torr and pulse repetition rate from 4 Hz to 180 Hz. As a result, the maximum average output was about 19.6W at the total pressure of 12 Torr and the pulse repetition rate of 180Hz.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.70-77
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• 2013

We suggest a low area and high efficiency switched-mode power supply (SMPS) with a pulse width modulation (PWM) generator based on a pseudo relaxation-oscillating technique. In the proposed circuit, the PWM duty ratio is determined by the voltage slope control of an internal capacitor according to amount of charging current in a PWM generator. Compared to conventional SMPSs, the proposed control method consists of a simple structure without the filter circuits needed for an analog-controlled SMPS or the digital compensator used by a digitally-controlled SMPS. The proposed circuit is able to operate at switching frequency of 1MHz~10MHz, as this frequency can be controlled from the selection of one of the internal capacitors in a PWM generator. The maximum current of the core circuit is 2.7 mA, and the total current of the entire circuit including output buffer driver is 15 mA at 10 MHz switching frequency. The proposed SMPS has a simulated maximum ripple voltage of 7mV. In this paper, to verify the operation of the proposed circuit, we performed simulation using Dongbu Hitek BCD $0.35{\mu}m$ technology and measured the proposed circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.100-105
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• 2010

A multi-band low noise amplifier (LNA) is designed in 90 nm RF CMOS process for 3GPP LTE (3rd Generation Partner Project Long Term Evolution) applications. The designed multi-band LNA covers the eight frequency bands between 1.85 and 2.8 GHz. A tunable input matching circuit is realized by adopting a switched capacitor array at the LNA input stage for providing optimum performances across the wide operating band. Current steering technique is adopted for the gain control in three steps. The performances of the LNA are verified through post-layout simulations (PLS). The LNA consumes 17 mA at 1.2 V supply voltage. It shows a power gain of 26 at the normal gain mode, and provides much lower gains of 0 and -6.7 in the bypass-I and -II modes, respectively. It achieves a noise figure of 1.78 dB and a IIP3 of -12.8 dBm over the entire band.

• Journal of Power Electronics
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• v.18 no.3
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• pp.841-852
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• 2018

This paper presents a dual-algorithm search method (GWO-GSO) combining grey wolf optimization (GWO) and golden-section optimization (GSO) to realize maximum power point tracking (MPPT) for photovoltaic (PV) systems. First, a modified grey wolf optimization (MGWO) is activated for the global search. In conventional GWO, wolf leaders possess the same impact on decision-making. In this paper, the decision weights of wolf leaders are automatically adjusted with hunting progression, which is conducive to accelerating hunting. At the later stage, the algorithm is switched to GSO for the local search, which play a critical role in avoiding unnecessary search and reducing the tracking time. Additionally, a novel restart judgment based on the quasi-slope of the power-voltage curve is introduced to enhance the reliability of MPPT systems. Simulation and experiment results demonstrate that the proposed algorithm can track the global maximum power point (MPP) swiftly and reliably with higher accuracy under various conditions.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.1 s.307
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• pp.45-52
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• 2006

In this paper, authors propose a step-up converter of pulse width modulation (PWM) and power factor correction (PFC) by using a novel loss-less snubber. The proposed converter for a discontinuous conduction mode (DCM) eliminates the complicated circuit control requirement and reduces the size of components. The input current waveform in the proposed converter is got to be a sinusoidal form of discontinuous pulse in proportion to magnitude of ac input voltage under the constant duty cycle switching. Thereupon, the input power factor is nearly unity and the control method is simple. In the general DCM converters, the switching devices are fumed-on with the zero current switching (ZCS), and the switching devices must be switched-off at a maximum reactor current. To achieve a soft switching (ZCS and ZVS) of the switching turn-off, the proposed converter is constructed by using a new loss-less snubber which is operated with a partial resonant circuit. The result is that the switching loss is very low and the efficiency of converter is high. Some simulative results on computer and experimental results are included to confirm the validity of the analytical results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.65-73
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• 2006

This work presents a 14b 200KS/s $0.87mm^2$ 1.2mW 0.18um CMOS algorithmic A/D converter (ADC) for intelligent sensors control systems, battery-powered system applications simultaneously requiring high resolution, low power, and small area. The proposed algorithmic ADC not using a conventional sample-and-hold amplifier employs efficient switched-bias power-reduction techniques in analog circuits, a clock selective sampling-capacitor switching in the multiplying D/A converter, and ultra low-power on-chip current and voltage references to optimize sampling rate, resolution, power consumption, and chip area. The prototype ADC implemented in a 0.18um 1P6M CMOS process shows a measured DNL and INL of maximum 0.98LSB and 15.72LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 54dB and 69dB, respectively, and a power consumption of 1.2mW at 200KS/s and 1.8V. The occupied active die area is $0.87mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.