• Journal of the Korean Institute of Telematics and Electronics
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• v.16 no.4
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• pp.36-46
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• 1979

Using N_ Ch silicon gate technology . the capacitors and transistors with various dimenssion were fabricated. Although the applied process was somewhat standard the conditions of ion implantation for the gate were varied by changing the implant energies from 30keV to 60keV for B and from 100 keV to 175keV for P . The doses of the implant also changed from 3 $\times$ 10 /$\textrm{cm}^2$ to 5 $\times$ 10 /$\textrm{cm}^2$ for B and from 4$\times$ 10 /$\textrm{cm}^2$ to 7 $\times$ 10 /$\textrm{cm}^2$ for P . The D. C. parameters such as threshold voltage. substrate doping level, the degree of inversion, capacitance. flat band voltage, depletion layer width, gate oxide thickless, surface states, motile charge density, electron mobility. leakage current were evaluated and also compared with the corresponing theoretical values and / or good numbers for application. The threshold voltages measured using curve tracer and C-V plot gave good agreements with the values calculated from SUPREM II which has been developed by Stanford University process group. The threshold vol tapes with back gate bias were used to calculate the change of the substrate doping level. The measured subthreshold slope enabled the prediction of the degree of inversion The D. C. testing results suggest the realized capacitors and transistors are suited for the memory applications.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1085-1087
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• 1995

A large leakage current may be one of the critical issues for poly-silicon thin film transistors(poly-Si TFTs) for LCD applications. In order to reduce the leakage current of poly-Si TFTs, several offset gated structures have been reported. However, those devices, where the offset length in the source region is not same as that in the drain region, exhibit the asymmetric electrical performances such as the threshold voltage shift and the variation of the subthreshold slope. The different offset length is caused by the additional mask step for the conventional offset structures. Also the self-aligned implantation may not be applicable due to the mis-alignment problem. In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photo resistor reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate from both sides of the main gate. The poly-Si channel layer below the offset oxide is protected from the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of our new device is the offset lesion due to the offset oxide. Our experimental results show that the offset region, due to the photo resistor reflow process, has been successfully obtained in order to fabricate the offset gated poly-Si TFTs. The advantages of the proposed device are that the offset length in the source region is the same as that in the drain region because of the self-aligned implantation and the proposed device does not require any additional mask process step.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.198-203
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• 2016

We investigate the effects of magnesium (Mg) suppressor layer on the electrical performances and stabilities of amorphous indium-zinc-tin-oxide (a-ITZO) thin-film transistors (TFTs). Compared to the ITZO TFT without a Mg suppressor layer, the ITZO:Mg TFT exhibits slightly smaller field-effect mobility and much reduced subthreshold slope. The ITZO:Mg TFT shows improved electrical stabilities compared to the ITZO TFT under both positive-bias and negative-bias-illumination stresses. From the X-ray photoelectron spectroscopy O1s spectra with fitted curves for ITZO and ITZO:Mg films, we observe that Mg doping contributes to an enhancement of the oxygen bond without oxygen vacancy and a reduction of the oxygen bonds with oxygen vacancies. This result shows that the Mg can be an effective suppressor in a-ITZO TFTs.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.324-326
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• 2016

In this study, we have investigated indium tin zinc oxide (ITZO) as an active channel for non-volatile memory (NVM) devices. The electrical and memory characteristics of NVM devices using multi-stack gate insulator SiO2/SiOx/SiOxNy (OOxOy) with Si-rich SiOx for charge storage layer were also reported. The transmittance of ITZO films reached over 85%. Besides, ITZO-based NVM devices showed good electrical properties such as high field effect mobility of 25.8 cm2/V.s, low threshold voltage of 0.75 V, low subthreshold slope of 0.23 V/dec and high on-off current ratio of $1.25{\times}107$. The transmission Fourier Transform Infrared spectroscopy of SiOx charge storage layer with the richest silicon content showed an assignment at peaks around 2000-2300 cm-1. It indicates that many silicon phases and defect sources exist in the matrix of the SiOx films. In addition, the characteristics of NVM device showed a retention exceeding 97% of threshold voltage shift after 104 s and greater than 94% after 10 years with low operating voltage of +11 V at only 1 ms programming duration time. Therefore, the NVM fabricated by high transparent ITZO active layer and OOxOy memory stack has been applied for the flexible memory system.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.267.1-267.1
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• 2016

본 연구에서는 nematic 액정의 종류 중 하나인 5CB (4-Cyano-4'-pentylbiphenyl) 물질을 박막 트랜지스터 (TFT)의 passivation 층으로 사용했을 때 그 전기적 특성향상을 확인하였다. RF-magnetron sputtering법으로 증착된 비정질 InGaZnO 박막을 활성층으로 사용한 TFT를 제작하여 그 활성층 위에 drop형식으로 passivation 하였다. 그 결과, drain current (I_DS)가 약 10배 정도 증가하고, linear region(V_D=0.5V)에서 mobility와 subthreshold slope(SS)이 각각 6.7에서 12.2, 0.3에서 0.2로 향상되는 것이 보였다. 이것은 gate bias가 인가되었을 때 freedericksz 전이를 통한 액정의 배향과 이때 형성된 dipole 형성에 의한 것으로 보이며, 이러한 LC의 배향은 편광현미경을 통하여 표면과 수직으로 배향한다는 사실을 확인 할 수 있었고 이 LC-passivation된 a-IGZO TFT의 전기적 특성의 향상에 대한 mechanism을 제시하였다. 그리고 배향한 LC가 가지는 dipole에 의해 bias stress 상황에서 독특한 electron trapping과 recovery의 증폭효과가 나타났다. V_G=+20V의 positive gate bias stress를 1000s동안 가했을 때, passivation되지 않은 a-IGZO TFT의 경우 +4V의 threshold voltage shift(${\Delta}V$_TH)가 발생되었고, 바로 -20V의 negative gate bias를 30s간 가해주었을 때 -2.5V의 ${\Delta}V$_TH가 발생하였다. 반면 LC-passivation된 a-IGZO TFT의 경우 각각 +5V와 -4V의 ${\Delta}V$_TH로 더 큰 변화를 가져왔다. 이러한 LC에 의한 electron trapping/recovery 증폭효과에 대한 model을 제시하였다.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.6
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• pp.235-240
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• 2003

In this paper, we present the fabrication and the characteristic analysis of sequential lateral solidification(SLS) poly-Si thin film transistors(TFT's) with molybdenum gate for active matrix liquid displays (AMLCD's) pixel controlling devices. The molybdenum gate is applied for the purpose of low temperature processing. The maximum processing temperature is 55$0^{\circ}C$ at the dopant thermal annealing step. The SLS processed poly-Si film which is reduced grain and grain boundary effect, is applied for the purpose of electrical characteristics improvements of poly-Si TFT's. The fabricated low temperature SLS poly-Si TFT's had a varying the channel length and width from 10${\mu}{\textrm}{m}$ to 2${\mu}{\textrm}{m}$. And to analyze these devices, extract electrical characteristic parameters (field effect mobility, threshold voltage, subthreshold slope, on off current etc) from current-voltage transfer characteristics curve. The extract electrical characteristic of fabricated low temperature SLS poly-Si TFT's showed the mobility of 100~400cm$^2$/Vs, the off current of about 100pA, and the on/off current ratio of about $10^7$. Also, we observed that the change of grain boundary according to varying channel length is dominant for the change of electrical characteristics more than the change of grain boundary according to varying channel width. Hereby, we comprehend well the characteristics of SLS processed poly-Si TFT's witch is recrystallized to channel length direction.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.6
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• pp.449-453
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• 2010

In this paper, the electrical characteristics of Fin-type SONOS(silicon-oxide-nitride-oxide-silicon) flash memory device with different trapping layers are analyzed in depth. Two kinds of trapping layers i.e., silicon nitride($Si_3N_4$) and hafnium oxide($HfO_2$) are applied. Compared to the conventional Fin-type SONOS device using the $Si_3N_4$ trapping layer, the Fin-type SOHOS(silicon-oxide-high-k-oxide-silicon) device using the $HfO_2$ trapping layer shows superior program/erase speed. However, the data retention properties in SOHOS device are worse than the SONOS flash memory device. Degraded data retention in the SOHOS device may be attributed to the tunneling leakage current induced by interface trap states, which are supported by the subthreshold slope and low frequency noise characteristics.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.7
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• pp.472-476
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• 2014

We report the characteristics of thin-film transistor (TFT) to make the bi-channel structure with stacked $Mg_{0.1}Zn_{0.9}O$ (Mg= 10 at.%) and ZnO. The ZnO and $Mg_{0.1}ZnO_{0.9}O$ thin films were deposited by radio frequency (RF) co-sputter system onto the thermally oxidized silicon substrate. A total thickness of active layer was 50 nm. Firstly, the ZnO thin films were deposited to control the thickness from 5 nm to 30 nm. Sequentially, the $Mg_{0.1}ZnO_{0.9}O$ thin films were deposited to change from 45 nm to 20 nm. The bi-layer TFT shows more improved properties than the single layer TFT. The field effect mobility and subthreshold slope for $Mg_{0.1}ZnO_{0.9}O$/ZnO-TFT are $7.40cm^2V^{-1}s^{-1}$ and 0.24 V/decade at the ZnO thickness of 10 nm, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.96-101
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• 2013

In this paper we analyzed the effects of polystyrene(PS) blended in TIPS-pentacene on the performance of OTFTs. With the various molecular weight and the content of PS the performance of TIPS-pentacene OTFTs was examined and the proper molecular weight and the content were extracted for the best results. With the molecular weight of 9,580 and 0.3 wt% of PS OTFTs produced the mobility of $1.0{\pm}0.19cm^2/V{\cdot}sec$, the subthreshold slope $0.22{\pm}0.05$ V/dec, the threshold voltage $-1.19{\pm}1.21$ V, the current on/of ratio $7.12{\pm}2.09{\times}10^6$. Additionally the suitable substrate temperature for ink jet printing of the blended TIPS-pentacene OTFTs was also extracted and it was $46^{\circ}C$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.2
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• pp.348-354
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• 2009

It has analyzed that the device degradation by NBTI (Negative Bias Temperature Instability) stress induced the increase of gate-induced-drain-leakage(GIDL) current for p-MOSFETs. It is shown that the degradation magnitude, as well as its time, temperature, and field dependence, is govern by interface traps density at the silicon/oxide interface. from the relation between the variation of threshold voltage and subthreshold slope, it has been found that the dominant mechanism for device degradation is the interface state generation. From the GIDL measurement results, we confined that the EHP generation in interface state due to NBTI stress led to the increase of GIDL current. Therefore, one should take care of the increased GIDL current after NBTI stress in the ultra-thin gate oxide device. Also, the simultaneous consideration of reliability characteristics and dc device performance is highly necessary in the stress engineering of nanoscale CMOSFETs.