• 한국전기전자재료학회논문지
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• 제24권6호
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• pp.473-479
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• 2011

In this paper, we have compared amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) with the nano-crystalline embedded-IGZO ($N_c$-embedded-IGZO) TFT fabricated by solid-phase crystallization (SPC) technique. The field effect mobility (${\mu}_{FE}$) of $N_c$-embedded-IGZO TFT was 2.37 $cm^2/Vs$ and the subthreshold slope (S-factor) was 0.83 V/decade, which showed lower performance than those of a-IGZO TFT (${\mu}_{FE}$ of a-IGZO was 9.67 $cm^2/Vs$ and S-factor was 0.19 V/decade). This results originated from generation of oxygen vacancies in oxide semiconductor and interface between gate insulator and semiconductor due to high temperature annealing process. However, the threshold voltage shift (${\Delta}V_{TH}$) of $N_c$-embedded-IGZO TFT was 0.5 V, which showed 1 V less shift than that of a-IGZO TFT under constant current stress during $10^5$ s. This was because there were additionally less increase of interface trap charges in Nc-embedded-IGZO TFT than a-IGZO TFT.

• 한국전기전자재료학회논문지
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• 제24권6호
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• pp.458-462
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• 2011

Soution-processed ZrInZnO (ZIZO) thin-film transistors (TFTs) with varying Zr content were fabricated. The ZIZO TFT (Zr=20 at. %/Zn) has an optimal performance with the saturation field effect mobility of 0.77 $cm^2/Vs$, the threshold voltage (Vth) of 2.1 V, the on/off ratio of $4.95{\times}10^6$, and subthreshold swing (S.S) of 0.73 V/decade. Using this optimized ZIZO TFT, the positive and negative gate bias stress according to annealing temperature was also investigated. While the Vth shifts dramatically after 1,000 s of both gate bias stresses, variations in the S.S are negligible. It suggests that electrons or holes are tem porarily trapped in the gate insulator, the semiconductor, or the interface between both layers.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.533-533
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• 2007

The stress effect of SiGe p-type metal oxide semiconductors field effect transistors(MOSFETs) has been investigated to compare device properties using Si bulk and partially depleted silicon on insulator(PD SOI). The electrical properties in SiGe PD SOI presented enhancements in subthreshold slope and drain induced barrier lowering in comparison to SiGe bulk. The reliability of gate oxides on bulk Si and PD SOI has been evaluated using constant voltage stressing to investigate their breakdown (~ 8.5 V) characteristics. Gate leakage was monitored as a function of voltage stressing time to understand the breakdown phenomena for both structures. Stress induced leakage currents are obtained from I-V measurements at specified stress intervals. The 1/f noise was observed to follow the typical $1/f^{\gamma}$ (${\gamma}\;=\;1$) in SiGe bulk devices, but the abnormal behavior ${\gamma}\;=\;2$ in SiGe PD SOI. The difference of noise frequency exponent is mainly attributed to traps at silicon oxide interfaces. We will discuss stress induced instability in conjunction with the 1/f noise characteristics in detail.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.241.2-241.2
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• 2013

최근, 비정질 산화물 반도체 thin film transistor (TFT)는 수소화된 비정질 실리콘 TFT와 비교하여 높은 이동도와 큰 on/off 전류비, 낮은 구동 전압을 가짐으로써 빠른 속도가 요구되는 차세대 투명 디스플레이의 TFT로 많은 연구가 진행되고 있다. 한편, 기존의 MOSFET 제작 시 우수한 박막을 얻기 위해서는 $500^{\circ}C$ 이상의 높은 열처리 온도가 필수적이며 이는 유리 기판과 플라스틱 기판에 적용하는 것이 적합하지 않고 높은 온도에서 수 시간 동안 열처리를 수행해야 하므로 공정 시간 및 비용이 증가하게 된다는 단점이 있다. 따라서, 본 연구에서는 RF sputter를 이용하여 증착된 비정질 InGaZnO pesudo MOSFET 소자를 제작하였으며, thermal 열처리와 microwave 열처리 방식에 따른 전기적 특성을 비교 및 분석하고 각 열처리 방식의 열처리 온도 및 조건을 최적화하였다. P-type bulk silicon 위에 산화막이 100 nm 형성된 기판에 RF 스퍼터링을 이용하여 InGaZnO 분말을 각각 1:1:2mol% 조성비로 혼합하여 소결한 타겟을 사용하여 70 nm 두께의 InGaZnO를 증착하였다. 연속해서 Photolithography 공정과 BOE(30:1) 습식 식각 과정을 이용해 활성화 영역을 형성하여 소자를 제작하였다. 제작 된 소자는 pseudo MOSFET 구조이며, 프로브 탐침을 증착 된 채널층 표면에 직접 접촉시켜 소스와 드레인 역할을 대체하여 동작시킬 수 있어 전기적 특성을 간단하고 간략화된 공정과정으로 분석할 수 있는 장점이 있다. 열처리 조건으로는 thermal 열처리의 경우, furnace를 이용하여 각각 $300^{\circ}C$, $400^{\circ}C$, $500^{\circ}C$, $600^{\circ}C$에서 30분 동안 N2 가스 분위기에서 열처리를 실시하였고, microwave 열처리는 microwave를 이용하여 각각 400 W, 600 W, 800 W, 1000 W로 20분 동안 실시하였다. 그 결과, furnace를 이용하여 열처리한 소자와 비교하여 microwave 를 통해 열처리한 소자에서 subthreshold swing (SS), threshold voltage (Vth), mobility 등이 개선되는 것을 확인하였다. 따라서, microwave 열처리 공정은 향후 저온 공정을 요구하는 MOSFET 제작 시의 훌륭한 대안으로 사용 될 것으로 기대된다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 추계학술대회 논문집
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• pp.506-508
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• 2005

In general, organic TFTs are comprised of four components: gate electrode, gate dielectric, organic active semiconductor layer, and source and drain contacts. The TFT current, in turn, is typically determined by channel length and width, carrier field effect mobility, gate dielectric thickness and permittivity, contact resistance, and biasing conditions. More recently, a number of techniques and processes have been introduced to the fabrication of OTFT circuits and displays that aim specifically at reduced fabrication cost. These include microcontact printing for the patterning of metals and dielectrics, the use of photochemically patterned insulating and conducting films, and inkjet printing for the selective deposition of contacts and interconnect pattern. In the fabrication of organic TFTs, microcontact printing has been used to pattern gate electrodes, gate dielectrics, and source and drain contacts with sufficient yield to allow the fabrication of transistors. We were fabricated a pentacene OTFTs on flexible PEN film. Au/Cr was used for the gate electrode, parylene-c was deposited as the gate dielectric, and Au/Cr was chosen for the source and drain contacts; were all deposited by ion-beam sputtering and patterned by microcontact printing and lift-off process. Prior to the deposition of the organic active layer, the gate dielectric surface was treated with octadecyltrichlorosilane(OTS) from the vapor phase. To complete the device, pentacene was deposited by thermal evaporation and patterned using a parylene-c layer. The device was shown that the carrier field effect mobility, the threshold voltage, the subthreshold slope, and the on/off current ratio were improved.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2014년도 춘계학술대회
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• pp.741-744
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• 2014

본 연구에서는 비대칭 이중게이트(double gate; DG) MOSFET의 하단 게이트전압에 대한 문턱전압이동 현상에 대하여 분석하였다. 비대칭 DGMOSFET는 4단자소자로서 상단과 하단의 게이트단자에 별도의 전압을 인가할 수 있으므로 하단게이트전압의 변화가 문턱전압에 영향을 미칠 것이다. 그러므로 단채널효과로 알려져 있는 문턱전압이동현상이 하단게이트전압에 의하여 감소할 수 있는지를 관찰하고자 한다. 이를 위하여 문턱전압 이하영역에서의 차단전류모델을 제시하였으며 차단전류가 채널폭 당 $10^{-7}A/{\mu}m$일 경우의 상단게이트 전압을 문턱전압으로 정의하여 채널길이 및 채널두께의 변화에 따라 하단게이트 전압의 변화에 대한 문턱전압의 이동현상을 관찰하였다. 결과적으로 하단게이트전압은 문턱전압이동현상에 커다란 영향을 미치는 것을 알 수 있었으며, 특히 단채널효과가 심각하게 발생하고 있는 채널길이 및 채널두께 영역에서는 더욱 큰 영향을 미치고 있다는 것을 알 수 있었다.

• Advances in nano research
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• 제10권5호
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• pp.415-422
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• 2021

Silicene, a 2D allotrope of silicon, is predicted to be a potential material for future transistor that might be compatible with present silicon fabrication technology. Similar to graphene, silicene exhibits the honeycomb lattice structure. Consequently, silicene is a semimetallic material, preventing its application as a field-effect transistor. Therefore, this work proposes the uniform doping bandgap engineering technique to obtain the n-type silicene nanosheet. By applying nearest neighbour tight-binding approach and parabolic band assumption, the analytical modelling equations for band structure, density of states, electrons and holes concentrations, intrinsic electrons velocity, and ideal ballistic current transport characteristics are computed. All simulations are done by using MATLAB. The results show that a bandgap of 0.66 eV has been induced in uniformly doped silicene with phosphorus (PSi₃NW) in the zigzag direction. Moreover, the relationships between intrinsic velocity to different temperatures and carrier concentration are further studied in this paper. The results show that the ballistic carrier velocity of PSi₃NW is independent on temperature within the degenerate regime. In addition, an ideal room temperature subthreshold swing of 60 mV/dec is extracted from ballistic current-voltage transfer characteristics. In conclusion, the PSi₃NW is a potential nanomaterial for future electronics applications, particularly in the digital switching applications.

• 대한금속재료학회지
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• 제50권8호
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• pp.613-618
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• 2012

We report on electrical and mechanical properties of silicon nitride ($SiN_x$) films deposited by a plasma enhanced chemical vapor deposition (PECVD) method at $200^{\circ}C$ from $SiH_4$ highly diluted in $N_2$. The films were also prepared from $SiH_4$ diluted in He for comparison. The $N_2$ dilution was also effective in improving adhesion of the $SiN_x$ films, fascilitating construction of thin film transistors (TFTs). Metal-insulator-semiconductor (MIS) and Metal-insulator-Metal (MIM) structures were used for capacitance-voltage (C-V) and current-voltage (I-V) measurements, respectively. The resistivity and breakdown field strength of the $SiN_x$ films from $N_2$-diluted $SiH_4$ were estimated to be $1{\times}10^{13}{\Omega}{\cdot}cm$, 7.4 MV/cm, respectively. The MIS device showed a hysteresis window and a flat band voltage shift of 3 V and 0.5 V, respectively. The TFTs fabricated by using these films showed a field-effect mobility of $0.16cm^2/Vs$, a threshold voltage of 3 V, a subthreshold slope of 1.2 V/dec, and an on/off ratio of > $10^6$.

• 한국정보전자통신기술학회논문지
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• 제15권5호
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• pp.335-342
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• 2022

본 논문에서는 오디오 애플리케이션을 위한 단일 비트 3차 피드포워드 델타 시그마 변조기를 제안한다. 제안된 변조기는 저전압 및 저전력 애플리케이션을 위한 클래스-C 인버터를 기반으로 한다. 고정밀 요구 사항을 위해 레귤레이티드 캐스코드 구조의 클래스-C 인버터는 DC 이득을 증가시키고 저전압 서브쓰레스홀드 증폭기 역할을 한다. 제안된 클래스-C 인버터 기반 변조기는 180nm CMOS 공정으로 설계 및 시뮬레이션되었다. 성능 손실이 없으면서 낮은 공급 전압 호환성을 가지도록 제안된 클래스-C 인버터 기반 스위치드 커패시터 변조기는 높은 전력 효율을 달성하였다. 본 설계는 20kHz의 신호 대역폭 및 4MHz의 샘플링 주파수에서 동작시켜 93.9dB의 SNDR, 108dB의 SNR, 102dB의 SFDR 및 102dB의 DR를 달성하면서 0.8V 전원 전압에서 280μW의 전력 소비만 사용한다.

• Advances in nano research
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• 제17권2호
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• pp.137-147
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• 2024

Graphene nanoribbons (GNRs) are considered a promising alternative to graphene for future nanoelectronic applications. However, GNRs-based device modeling is still at an early stage. This research models the electronic properties of n-doped rough-edged 13-armchair graphene nanoribbons (13-AGNRs) and quantum transport properties of n-doped rough-edged 13-armchair graphene nanoribbon field-effect transistors (13-AGNRFETs) at different doping concentrations. Step-up and edge doping are used to incorporate doping within the nanostructure. The numerical real-space nearest-neighbour tight-binding (NNTB) method constructs the Hamiltonian operator matrix, which computes electronic properties, including the sub-band structure and bandgap. Quantum transport properties are subsequently computed using the self-consistent solution of the two-dimensional Poisson and Schrödinger equations within the non-equilibrium Green's function method. The finite difference method solves the Poisson equation, while the successive over-relaxation method speeds up the convergence process. Performance metrics of the device are then computed. The results show that highly doped, rough-edged 13-AGNRs exhibit a lower bandgap. Moreover, n-doped rough-edged 13-AGNRFETs with a channel of higher doping concentration have better gate control and are less affected by leakage current because they demonstrate a higher current ratio and lower off-current. Furthermore, highly n-doped rough-edged 13-AGNRFETs have better channel control and are less affected by the short channel effect due to the lower value of subthreshold swing and drain-induced barrier lowering. The inclusion of dopants enhances the on-current by introducing more charge carriers in the highly n-doped, rough-edged channel. This research highlights the importance of optimizing doping concentrations for enhancing GNRFET-based device performance, making them viable for applications in nanoelectronics.