• 제목/요약/키워드: sub-micron

검색결과 313건 처리시간 0.023초

Reduction of Plasma Process Induced Damage during HDP IMD Deposition

  • Kim, Sang-Yung;Lee, Woo-Sun;Seo, Yong-Jin
    • Transactions on Electrical and Electronic Materials
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    • 제3권3호
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    • pp.14-17
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    • 2002
  • The HDP (High Density Plasma) CVD process consists of a simultaneous sputter etch and chemical vapor deposition. As CMOS process continues to scale down to sub- quarter micron technology, HDP process has been widely used fur the gap-fill of small geometry metal spacing in inter-metal dielectric process. However, HBP CVD system has some potential problems including plasma-induced damage. Plasma-induced gate oxide damage has been an increasingly important issue for integrated circuit process technology. In this paper, thin gate oxide charge damage caused by HDP deposition of inter-metal dielectric was studied. Multiple step HDP deposition process was demonstrated in this work to prevent plasma-induced damage by introducing an in-situ top SiH$_4$ unbiased liner deposition before conventional deposition.

Development of Porous Metal Materials and Applications

  • Fang, Y.;Wang, H.;Zhou, Y.;Kuang, C.
    • 한국분말야금학회:학술대회논문집
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    • 한국분말야금학회 2006년도 Extended Abstracts of 2006 POWDER METALLURGY World Congress Part 1
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    • pp.599-600
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    • 2006
  • This paper described the state of art of porous metal materials, the typical manufacturing technologies and performances of sintered metal porous materials, with emphasis on the recent research achievements of CISRI in development of porous metal materials. High performance porous metal materials, such as metallic membrane, sub-micron asymmetric composite porous metal, large dimensional and structure complicated porous metal aeration cones and tube, metallic catalytic filter elements, lotus-type porous materials, etc, have been developed. Their applications in energy industry, petrochemical industry, clean coal process and other industrial fields were introduced and discussed.

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Characteristics of Porous YAG Powders Fabricated by PVA Polymer Solution Technique

  • Lee, S.J.;Shin, P.W.;Kim, J.W.;Chun, S.Y.
    • 한국분말야금학회:학술대회논문집
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    • 한국분말야금학회 2006년도 Extended Abstracts of 2006 POWDER METALLURGY World Congress Part 1
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    • pp.438-439
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    • 2006
  • Pure and stable YAG $(Y_3Al_5O_{12})$ powders were synthesized by a PVA (polyvinyl alcohol) polymer solution technique. PVA was used as an organic carrier for the precursor ceramic gel. The precursor gels were crystallized to YAG at relatively a low temperature of $900\;^{\circ}C$. The synthesized powders, which have nano-sized primary particles, were soft and porous, and the porous powders were ground to sub-micron size by a simple ball milling process. The ball-milled powders were densified to 94% relative density at $1500\;^{\circ}C$ for 1h. In this study, the characteristics of the synthesized YAG powders were examined.

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산화제 첨가에 따른 $WO_3$ 박막의 CMP 특성 (Characteristic of Addition Oxidizer on the $WO_3$ Thin Film CMP)

  • 이우선;고필주;최권우;김태완;최창주;오금곤;서용진
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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    • pp.313-316
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    • 2004
  • Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of in the defect-free inter-level dielectrics(ILD). we investigated the performance of $WO_3$ CMP used silica slurry, ceria slurry, tungsten slurry In this paper, the effects of addition oxidizer on the $WO_3$ CMP characteristics were investigated to obtain the higher removal rate and lower non-uniformity.

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$WO_3$ CMP의 광역평탄화 특성 (Global planarization Characteristic of $WO_3$ CMP)

  • 이우선;고필주;최권우;이영식;서용진
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
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    • pp.188-191
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    • 2003
  • Chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of in the defect-free inter-level dielectrics (ILD). we investigated the performance of $WO_3$ CMP used silica slurry, ceria slurry, tungsten slurry. In this paper, the effects of addition oxidizer on the $WO_3$ CMP characteristics were investigated to obtain the higher removal rate and lower non-uniformity.

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초고집적소자의 층간절연막용 polysilazane계 spin on glass (SOG)에 관한 연구 (A study on the spin on glass (SOG) from polysilazane resin for the premetal dielectric (PMD) layer of sub-quarter micron devices)

  • 나사균;정석철;이재관;김진우;홍정의;이원준
    • 한국진공학회지
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    • 제9권1호
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    • pp.69-75
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    • 2000
  • We have investigated the feasibility of spin on glass (SOG) film from polysilazane-type resin as a premetal dielectric (PMD) layer of the next-generation ultra-large scale integrated (ULSI) devices. A commercial polysilazane resin and a polysilazane-type resin with oxidizing agent were spin-coated and cured to form SOG films. In order to study the effect of oxidizing agent and annealing, the SOG films were characterized as cured and after annealing at $400^{\circ}C$ to $900^{\circ}C$. the density and the resistance against wet chemical of the SOG films were improved by the addition of oxidizing agent, because oxidizing agent enhanced the conversion from polysilazane polymer to $SiO_2$. The hole profile issue associated with insufficient curing of polysilazane in narrow gaps was also resolved by oxidizing agent, while the gapfill capability of SOG was not deteriorated by oxidizing agent.

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온칩 메모리 내 다중 비트 이상에 대처하기 위한 오류 정정 부호 (Error correction codes to manage multiple bit upset in on-chip memories)

  • Jun, Hoyoon
    • 한국정보통신학회논문지
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    • 제26권11호
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    • pp.1747-1750
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    • 2022
  • As shrinking the semiconductor process into the deep sub-micron to achieve high-density, low power and high performance integrated circuits, MBU (multiple bit upset) by soft errors is one of the major challenge of on-chip memory systems. To address the MBU, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not resolve mis-correction. We propose the SEC-DED-DAEC-TAED(triple adjacent error detection) code without mis-corrections. The generated H-matrix by the proposed heuristic algorithm to accomplish the proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the 2-stage pipelined decoder can be employed on-chip memory system.

고에너지 분쇄 매체 지르코니아 Beads의 미세구조 및 기계적 특성에 따른 마모율 분석 (Analysis of Attrition Rate of Y2O3 Stabilized Zirconia Beads with Different Microstructure and Mechanical Properties)

  • 김정환;윤세중;한병동;안철우;윤운하;최종진
    • 한국재료학회지
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    • 제28권6호
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    • pp.349-354
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    • 2018
  • Particle size reduction is an important step in many technological operations. The process itself is defined as the mechanical breakdown of solids into smaller particles to increase the surface area and induce defects in solids, which are needed for subsequent operations such as chemical reactions. To fabricate nano-sized particles, several tens to hundreds of micron size ceramic beads, formed through high energy milling process, are required. To minimize the contamination effects during high-energy milling, the mechanical properties of zirconia beads are very important. Generally, the mechanical properties of $Y_2O_3$ stabilized tetragonal zirconia beads are closely related to the mechanism of phase change from tetragonal to monoclinic phase via external mechanical forces. Therefore, $Y_2O_3$ distribution in the sintered zirconia beads must also be closely related with the mechanical properties of the beads. In this work, commercially available $100{\mu}m-size$ beads are analyzed from the point of view of microstructure, composition homogeneity (especially for $Y_2O_3$), mechanical properties, and attrition rate.

STI를 이용한 서브 0.1$\mu\textrm{m}$VLSI CMOS 소자에서의 초박막게이트산화막의 박막개선에 관한 연구 (A study on Improvement of sub 0.1$\mu\textrm{m}$VLSI CMOS device Ultra Thin Gate Oxide Quality Using Novel STI Structure)

  • 엄금용;오환술
    • 한국전기전자재료학회논문지
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    • 제13권9호
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    • pp.729-734
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    • 2000
  • Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

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Visible-Light-Driven Catalytic Disinfection of Staphylococcus aureus Using Sandwich Structure g-C3N4/ZnO/Stellerite Hybrid Photocatalyst

  • Zhang, Wanzhong;Yu, Caihong;Sun, Zhiming;Zheng, Shuilin
    • Journal of Microbiology and Biotechnology
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    • 제28권6호
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    • pp.957-967
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    • 2018
  • A novel $g-C_3N_4$/ZnO/stellerite (CNZOS) hybrid photocatalyst, which was synthesized by coupled hydro thermal-thermal polymerization processing, was applied as an efficient visible-light-driven photocatalyst against Staphylococcus aureus. The optimum synthesized hybrid photocatalyst showed a sandwich structure morphology with layered $g-C_3N_4$ (doping amount: 40 wt%) deposited onto micron-sized ZnO/stellerite particles (ZnO average diameter: ~18 nm). It had a narrowing band gap (2.48 eV) and enlarged specific surface area ($23.05m^2/g$). The semiconductor heterojunction effect from ZnO to $g-C_3N_4$ leads to intensive absorption of the visible region and rapid separation of the photogenerated electron-hole pairs. In this study, CNZOS showed better photocatalytic disinfection efficiency than $g-C_3N_4/ZnO$ powders. The disinfection mechanism was systematically investigated by scavenger-quenching methods, indicating the important role of $H_2O_2$ in both systems. Furthermore, $h^+$ was demonstrated as another important radical in oxidative inactivation of the CNZOS system. In respect of the great disinfection efficiency and practicability, the CNZOS heterojunction photocatalyst may offer many disinfection applications.