• 제목/요약/키워드: stuck problem

검색결과 34건 처리시간 0.024초

CMOS 회로의 Stuck-open 고장검출을 위한 로보스트 테스트 생성 (Robust Test Generation for Stuck-Open Faults in CMOS Circuits)

  • 정준모;임인칠
    • 대한전자공학회논문지
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    • 제27권11호
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    • pp.42-48
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    • 1990
  • 본 논문에서는 CMOS 회로의 stuck-open 고장 검출을 위한 로브스트(robust)테스트 생성방법을 제안한다. CMOS 회로에 대한 입력 벡터들간의 비트(bit)위치와 해밍중(Hamming weight)의 관계를 고려하여 초기화 패턴을 구함으로써 stuck-open 고장검출을 위한 테스트 생성 시간을 감소시킬 수 있으며, 고장검출을 어렵게하게 하는 입력변이지연(input transition skew)의 문제를 해결하고, 테스트 사이퀸스의 수를 최소화시킨다. 또한 회로에 인가할 초기화 패턴과 테스트 패턴간의 해밍거리(hamming distance)를 고려하여 테스트 사이퀸스를 배열하므로써 테스트 사이퀸스의 수를 감소시킨다.

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domino CMOS 논리회로의 테스트 생성에 관한 연구 (A Study on Test Generation for Domino CMOS Logic Circuits)

  • 이재민;이준모;정준모
    • 대한전자공학회논문지
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    • 제27권7호
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    • pp.1118-1127
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    • 1990
  • In this paper a new test generation method for Domino CMOS logic circuits is proposed. Because the stuck-at type fault is not adequate for Domino CMOS circuits the stuck-open fault, stuck-on fault and bridging fault are considered as fault models. It is shown that the test generation problem of Domino CMOS circuits results in functional block test generation problem. Test set is generated by using the logic minimizer which is a part of logic design system. An algorithm for reduction of test set is described. The proposed test method can be easily applied to various figures of circuits and make it easy to construct automatic test generator in design system. The proposed algorithms are programed and their efficiency is confirmed by examples.

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디지털 CMOS 회로의 Multi-Level Test를 위한 범용 Test Set 생성 (Universal Test Set Generation for Multi-Level Test of Digital CMOS Circuits)

  • Dong Wook Kim
    • 전자공학회논문지A
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    • 제30A권2호
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    • pp.63-75
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    • 1993
  • As the CMOS technology becomes the most dominant circuit realization method, the cost problem for the test which includes both the transistor-level FET stuck-on and stuck-off faults and the gatelevel stuck-at faults becomes more and more serious. In accordance, this paper proposes a test set and its generation algorithm, which handles both the transistor-level faults and the gate-level faults, thus can unify the test steps during the IC design and fabrication procedure. This algorithm uses only the logic equation of the given logic function as the input resource without referring the transistor of gate circuit. Also, the resultant test set from this algorithm can improve in both the complexity of the generation algorithm and the time to apply the test as well as unify the test steps in comparing the existing methods.

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마이크로프로세서를 이용한 AOC 방식에서 EOG 앰프 성능 개선 (Improvement of the performance of EOC Amp in AOC method using microprocessor)

  • 고석남;이상세;정호춘;임승관;이영석;진달복;박병림
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 하계종합학술대회 논문집(5)
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    • pp.218-221
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    • 2000
  • The electronystagmography(ENG) means to measure and record CRP(Corneal-Retinal Potential) whenever the eyeball is moved by using a skin electrode stuck to the hi-temporal and the difference of CRP. Both the horizontal and vertical movement are known according to the position of the stuck skin electrode. In this paper, the variable time-constances to record the eyeball signal of the conventional EOG(Electro-Oculograph) Amplifier is chosen. The shorter the time-constance is, the worse the distortion of a signal is. But the unbalanced impedance of the electrode stuck on the hi-temporal is reduced. Also, the longer the time-constance is, the less the distortion of it signal is. But it is sensitive to the change of base line according to the unbalanced impedance. In order to solve these problems, an DC-Amplifier, the distortion of the eyeball signal is globally used. By solving unbalanced impedance problem of EOG amplifier, the distortion ratio of EOG amplifier is improved.

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오류 역전파 학습에서 확률적 가중치 교란에 의한 전역적 최적해의 탐색 (Searching a global optimum by stochastic perturbation in error back-propagation algorithm)

  • 김삼근;민창우;김명원
    • 전자공학회논문지C
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    • 제35C권3호
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    • pp.79-89
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    • 1998
  • The Error Back-Propagation(EBP) algorithm is widely applied to train a multi-layer perceptron, which is a neural network model frequently used to solve complex problems such as pattern recognition, adaptive control, and global optimization. However, the EBP is basically a gradient descent method, which may get stuck in a local minimum, leading to failure in finding the globally optimal solution. Moreover, a multi-layer perceptron suffers from locking a systematic determination of the network structure appropriate for a given problem. It is usually the case to determine the number of hidden nodes by trial and error. In this paper, we propose a new algorithm to efficiently train a multi-layer perceptron. OUr algorithm uses stochastic perturbation in the weight space to effectively escape from local minima in multi-layer perceptron learning. Stochastic perturbation probabilistically re-initializes weights associated with hidden nodes to escape a local minimum if the probabilistically re-initializes weights associated with hidden nodes to escape a local minimum if the EGP learning gets stuck to it. Addition of new hidden nodes also can be viewed asa special case of stochastic perturbation. Using stochastic perturbation we can solve the local minima problem and the network structure design in a unified way. The results of our experiments with several benchmark test problems including theparity problem, the two-spirals problem, andthe credit-screening data show that our algorithm is very efficient.

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신호선의 상관관계를 고려한 개선된 테스트용이도 분석 알고리즘 (An Improvement on Testability Analysis by Considering Signal Correlation)

  • 김윤홍
    • 한국산학기술학회논문지
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    • 제4권1호
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    • pp.7-12
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    • 2003
  • 테스트용이도(testability)분석은 논리회로에서 발생하는 stuck-at고장을 테스트하는 것이 어느 정도 어려운가를 예측 평가하기 위한 목적에서 이루어진다. 좋은 테스트용이도 분석 프로그램이 있다면, 회로의 테스트용이도를 개선하기 위한 좋은 방안을 회로 설계자들에게 사전에 제시해줌으로써, 테스트 문제에 미리 대비할 수 있도록 해준다. 그 동안 테스트용이도 분석을 효율적으로 수행하기 위한 연구가 있었다. 그러나 COP이나 SCOAP과 같은 기존의 대표적인 테스프용이도 분석 알괴리즘들은 트리 구조를 갖는 회로의 경우에 각 stuck-at고장의 테스트용이도 값을 효율적으로 계산할 수 있으나, 일반적인 구조의 회로에 대해서는 정확도가 떨어진다. 그 이유는 테스트용이도 분석을 선형적인 시간 내에 수행하기 위해서 각 신호신들은 재수렴 팬아웃(reconvergent fanout)으로 인한 상관관계가 없는 것으로 가정하기 때문이다. 본 논문에서는 테스트용이도 분석을 위해 신호선 상관관계를 고려한 개선된 방법을 제안한다. 제안된 방법에서는, 회로 내에서 재수렴 팬아웃과 이에 경향을 받는 게이트들에 대한 정보를 사전에 파악하기 위한 재수렴 팬아웃 분석 알고리즘을 이용하여, 재수렴 팬아웃으로 인한 효과를 테스트용이도 분석에 반영함으로써 정확도를 높이고 있다.

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위치기반 무선 센서 네트워크를 위한 보이드(void) 회피 라우팅 프로토콜 (Void-less Routing Protocol for Position Based Wireless Sensor Networks)

  • ;제갈찬;이채우
    • 대한전자공학회논문지TC
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    • 제45권10호
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    • pp.29-39
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    • 2008
  • 위치 기반의 라우팅 기법을 사용하는 센서 네트워크에서는 구현이 간단한 그리디(greedy) 라우팅이 흔히 사용된다. 그리디 라우팅은 센서 노드의 밀도가 높은 곳에는 잘 동작하지만 그렇지 않은 곳에서는 라우팅이 실패할 가능성이 크다. 그리디 라우팅 실패 시에는 패킷을 보이드(void)로부터 빠져나오게 하는 별도의 회복(recovery) 알고리즘이 필요하고 이러한 추가적인 알고리즘은 패킷의 송수신 양과 센서의 에너지 소비량을 증가시키는 문제를 발생시킨다. 여기서 언급한 보이드란 전송할 패킷을 가진 노드가 자신보다 목적지 노드에 더 가까운 이웃 노드를 찾지 못하여 그리디 포워딩으로 더 이상 패킷을 전송하지 못하는 지역을 의미한다. 따라서 본 논문은 보이드로 인한 라우팅 문제점들을 개선하기 위해 VODUA(Virtually Ordered Distance Upgrade Algorithm)라는 효율적인 라우팅 알고리즘을 제안한다. VODUA에서는 연결 정보를 나타내는 라우팅 그래프를 노드끼리 서로 교환하고, 패킷 전송이 불가능한 노드인 stuck 노드가 발생하면 거리 비용(DC)을 사용하여 네트워크 내의 stuck 노드를 제거한다. 본 논문에서는 거리 비용을 증가시켜 stuck 노드의 패킷이 보이드를 회피하여 원하는 목적지 노드까지 성공적으로 전송할 수 있도록 하는 새로운 방식의 라우팅 알고리즘을 설명한다. 또한 회복 알고리즘과 같은 추가적인 알고리즘 없이도 패킷이 전송 가능 한 경로를 가질 수 있도록 설계하여 기존의 라우팅 기법보다 더 빠르고 적은 에너지 소모를 통해 라우팅한다. 그리고 VODUA에서는 각각의 노드들이 네트워크 전체가 아닌 한 홉(hop) 이내에서 라우팅하고 토폴로지 상태정보를 사용하지 않기 때문에 노드의 실패(failure)나 토폴로지 변화에 적응이 빠르다. 시뮬레이션 결과는 VODUA가 짧은 전송 지연 시간을 통하여 신속하게 패킷을 전송할 수 있음을 보인다. 또한 GPSR과 DUA에 대해 더 적은 홉 수를 가지는 경로로 패킷이 전송 가능함을 보인다.

Fail safe and restructurable flight control system

  • Kanai, K.;Ochi, Y.
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 1994년도 Proceedings of the Korea Automatic Control Conference, 9th (KACC) ; Taejeon, Korea; 17-20 Oct. 1994
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    • pp.21-29
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    • 1994
  • This paper presents a method to accommodate failures that affect aircraft dynamical characteristics, especially control surface jams on a large transport aircraft. The approach is to use the slow effectors, such as the stabilators or engines, in the feedforward manner. The simulation results indicate the performance of the RFCS. In some cases of control surface jam, the aircraft cannot recover without using the stabilators. Although the inputs to the slow effectors are determined using the nominal parameters, the effects of parameter change can be compensated by adjusting the control parameters for the fast surfaces. In the case of rudder jam, if the remaining control surfaces and the differential thrust cancel the moments produced by the stuck rudder, using the engine control improves time responses and reduces deflection angles of the control surfaces. If not, however, the aircraft starts a large rolling motion following a yawing motion. In that case, the stabilators should be used to damp the induced rolliig motion, instead of trying to directly cancel the moments caused by the stuck rudder. Unfortunately, the proposed control law for the stabilators does not give such inputs, because it does not take into account the dynamical effects which stuck surfaces have on the aircraft motions. However, we have shown through simulation that the aircraft can be recovered by giving the stabilators the control inputs that counteract the induced rolling moment. Besides, the method has also been shown through simulation to be effective in maintaining control during a situation similar to an actual accident. Finally let us mention a problem with the RFCS. As stated above, we have not established a method to select a trim point which call be reached as easily as possible using the remaining control effectors. In fact, recovery performance considerably depends on the trim states. As pointed out in Ref. 11, finding the best trim point for impaired aircraft will be one of the most difficult questions in RFCS design.

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A 500 MHz-to-1.2 GHz Reset Free Delay Locked Loop for Memory Controller with Hysteresis Coarse Lock Detector

  • Chi, Han-Kyu;Hwang, Moon-Sang;Yoo, Byoung-Joo;Choe, Won-Jun;Kim, Tae-Ho;Moon, Yong-Sam;Jeong, Deog-Kyoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제11권2호
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    • pp.73-79
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    • 2011
  • This paper describes a reset-free delay-locked loop (DLL) for a memory controller application, with the aid of a hysteresis coarse lock detector. The coarse lock loop in the proposed DLL adjusts the delay between input and output clock within the pull-in range of the main loop phase detector. In addition, it monitors the main loop's lock status by dividing the input clock and counting its multiphase edges. Moreover, by using hysteresis, it controls the coarse lock range, thus reduces jitter. The proposed DLL neither suffers from harmonic lock and stuck problems nor needs an external reset or start-up signal. In a 0.13-${\mu}m$ CMOS process, post-layout simulation demonstrates that, even with a switching supply noise, the peak-to-peak jitter is less than 30 ps over the operating range of 500-1200 MHz. It occupies 0.04 $mm^2$ and dissipates 16.6 mW at 1.2 GHz.

Numerical convergence and validation of the DIMP inverse particle transport model

  • Nelson, Noel;Azmy, Yousry
    • Nuclear Engineering and Technology
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    • 제49권6호
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    • pp.1358-1367
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    • 2017
  • The data integration with modeled predictions (DIMP) model is a promising inverse radiation transport method for solving the special nuclear material (SNM) holdup problem. Unlike previous methods, DIMP is a completely passive nondestructive assay technique that requires no initial assumptions regarding the source distribution or active measurement time. DIMP predicts the most probable source location and distribution through Bayesian inference and quasi-Newtonian optimization of predicted detector responses (using the adjoint transport solution) with measured responses. DIMP performs well with forward hemispherical collimation and unshielded measurements, but several considerations are required when using narrow-view collimated detectors. DIMP converged well to the correct source distribution as the number of synthetic responses increased. DIMP also performed well for the first experimental validation exercise after applying a collimation factor, and sufficiently reducing the source search volume's extent to prevent the optimizer from getting stuck in local minima. DIMP's simple point detector response function (DRF) is being improved to address coplanar false positive/negative responses, and an angular DRF is being considered for integration with the next version of DIMP to account for highly collimated responses. Overall, DIMP shows promise for solving the SNM holdup inverse problem, especially once an improved optimization algorithm is implemented.