• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.243-246
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• 1999

We studied the MOSFET characteristics and the hot-carrier reliability with the sidewall spacer composition and the post gate oxidation thickness in 0.20${\mu}{\textrm}{m}$ gate length transistor. The MOSFET with NO(Nitride＋Oxide) sidewall spacer exhibits the large degradation of hot-carrier lifetime because there is no buffering oxide against nitride stress. When the post gate oxidation is skipped, the hot-carrier lifetime is improved, but GIDL (Gate Induced Drain Leakage) current is also increased.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.19-26
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• 2010

We found that saturated water vapor pressure is the most dominant stress factor for the degradation phenomenon in the package for high-power phosphor-converted white light emitting diode (high power LED). Also, we proved that saturated water vapor pressure is effective acceleration stress of LED package degradation from an acceleration life test. Test conditions were $121^{\circ}C$, 100% R.H., and max. 168 h storage with and without 350 mA. The accelerating tests in both conditions cause optical power loss, reduction of spectrum intensity, device leakage current, and thermal resistance in the package. Also, dark brown color and pore induced by hygro-mechanical stress partially contribute to the degradation of LED package. From these results, we have known that the saturated water vapor pressure stress is adequate as the acceleration stress for shortening life test time of LED packages.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.196-197
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• 2010

NAND형 charge trap flash (CTF) non-volatile memory (NVM) 소자가 30nm node 이하로 고집적화 되면서, 기존의 SONOS형 CTF NVM의 tunnel barrier로 쓰이는 SiO2는 direct tunneling과 stress induced leakage current (SILC)등의 효과로 인해 data retention의 감소 등 물리적인 한계에 이르렀다. 이에 따라 개선된 retention과 빠른 쓰기/지우기 속도를 만족시키기 위해서 tunnel barrier engineering (TBE)가 제안되었다. TBE NVM은 tunnel layer의 전위장벽을 엔지니어드함으로써 낮은 전압에서 전계의 민감도를 향상 시켜 동일한 두께의 단일 SiO2 터널베리어 보다 빠른 쓰기/지우기 속도를 확보할 수 있다. 또한 최근에 각광받는 high-k 물질을 TBE NVM에 적용시키는 연구가 활발히 진행 중이다. 본 연구에서는 Si3N4와 HfAlO (HfO2 : Al2O3 = 1:3)을 적층시켜 staggered의 새로운 구조의 tunnel barrier Capacitor를 제작하여 전기적 특성을 후속 열처리 온도와 방법에 따라 평가하였다. 실험은 n-type Si (100) wafer를 RCA 클리닝 실시한 후 Low pressure chemical vapor deposition (LPCVD)를 이용하여 Si3N4 3 nm 증착 후, Atomic layer deposition (ALD)를 이용하여 HfAlO를 3 nm 증착하였다. 게이트 전극은 e-beam evaporation을 이용하여 Al를 150 nm 증착하였다. 후속 열처리는 수소가 2% 함유된 질소 분위기에서 $300^{\circ}C$와 $450^{\circ}C$에서 Forming gas annealing (FGA) 실시하였고 질소 분위기에서 $600^{\circ}C{\sim}1000^{\circ}C$까지 Rapid thermal annealing (RTA)을 각각 실시하였다. 전기적 특성 분석은 후속 열처리 공정의 온도와 열처리 방법에 따라 Current-voltage와 Capacitance-voltage 특성을 조사하였다.

• Applied Science and Convergence Technology
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• v.26 no.5
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• pp.133-138
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• 2017

We investigated the interface defect engineering and reaction mechanism of reduced transition layer and nitride layer in the active plasma process on 4H-SiC by the plasma reaction with the rapid processing time at the room temperature. Through the combination of experiment and theoretical studies, we clearly observed that advanced active plasma process on 4H-SiC of oxidation and nitridation have improved electrical properties by the stable bond structure and decrease of the interfacial defects. In the plasma oxidation system, we showed that plasma oxide on SiC has enhanced electrical characteristics than the thermally oxidation and suppressed generation of the interface trap density. The decrease of the defect states in transition layer and stress induced leakage current (SILC) clearly showed that plasma process enhances quality of $SiO_2$ by the reduction of transition layer due to the controlled interstitial C atoms. And in another processes, the Plasma Nitridation (PN) system, we investigated the modification in bond structure in the nitride SiC surface by the rapid PN process. We observed that converted N reacted through spontaneous incorporation the SiC sub-surface, resulting in N atoms converted to C-site by the low bond energy. In particular, electrical properties exhibited that the generated trap states was suppressed with the nitrided layer. The results of active plasma oxidation and nitridation system suggest plasma processes on SiC of rapid and low temperature process, compare with the traditional gas annealing process with high temperature and long process time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.11
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• pp.1179-1185
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• 1991

Ultrathin Reoxidized Nitrided Oxides were formed by lamp heated rapid thermal annealing in oxyzen at temperatures of $1050^{\circ}C$-$1100^{\circ}C$ for 20, 40 seconds. The electrical characteristics of ultrathin films were evaluated by leakage current breakdown voltage. TDDB. FN tunneling. Nitridation and reoxidition condition dependence of charge trapping properties. i.e.. the flat band voltage shift $({\Delta}V_{FB})$ and the increase of charge-to-breakdown $(Q_{BD})$ induced by a high field stress where studied. As the results of analysis. rapid thermal reoxidation was achieved striking improvement of dielectric integrity, the charge to breakdown was increased and flat band voltage shift was reduced.

• The KIPS Transactions:PartA
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• v.15A no.4
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• pp.211-216
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• 2008

In this paper we fabricated and measured the $0.26{\mu}m$ NMOSFET with wet gate oxide and nitride oxide gate to compare that the charateristics of hot carrier effect, charge to breakdown, transistor Id_Vg curve, charge trapping, and SILC(Stress Induced Leakage Current) using the HP4145 device tester. As a result we find that the characteristics of nitride oxide gate device better than wet gate oxide device, especially hot carrier lifetime(nitride oxide gate device satisfied 30 years, but the lifetime of wet gate oxide was only 0.1 year), variation of Vg, charge to breakdown, electric field simulation and charge trapping etc.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.2
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• pp.23-30
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• 2012

This paper proposes a novel adaptive header-based power gating structure to compensate for the performance loss and the increased wake-up time of the power gating structures induced by the negative bias temperature instability (NBTI) effect. The proposed structure consists of variable width footers based on the two-pass power gating and a new NBTI sensing circuit for an adaptive control. The simulation results of the proposed structure are compared to those of power gating without the adaptive control and show that both the circuit-delay and wake-up time dependence of the power gating structure on the NBTI stress is minimized with only 3% and 4% increase, respectively while keeping small leakage power and rush-current. In this paper, a 45 nm CMOS technology and predictive NBTI model have been used to implement the proposed circuits.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.12
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• pp.939-943
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• 2011

In this paper, reliability of the two sandwiched MIM capacitors of $Al_2O_3-HfO_2-Al_2O_3$ (AHA) and $SiO_2-HfO_2-SiO_2$ (SHS) with hafnium-based dielectrics was analyzed using two kinds of voltage stress; DC and AC voltage stresses. Two MIM capacitors have high capacitance density (8.1 fF/${\mu}m^2$ and 5.2 fF/${\mu}m^2$) over the entire frequency range and low leakage current density of ~1 nA/$cm^2$ at room temperature and 1 V. The charge trapping in the dielectric shows that the relative variation of capacitance (${\Delta}C/C_0$) increases and the variation of voltage linearity (${\alpha}$/${\alpha}_0$) gradually decreases with stress-time under two types of voltage stress. It is also shown that DC voltage stress induced greater variation of capacitance density and voltage linearity than AC voltage stress.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.193.2-193.2
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• 2016

We evaluate the change in defects in the oxidized SiO2 grown on 4H-SiC (0001) by plasma assisted oxidation, by comparing with that of conventional thermal oxide. In order to investigate the changes in the electronic structure and electrical characteristics of the interfacial reaction between the thin SiO2 and SiC, x-ray photoelectron spectroscopy (XPS), X-ray absorption spectroscopy (XAS), DFT calculation and electrical measurements were carried out. We observed that the direct plasma oxide grown at the room temperature and rapid processing time (300 s) has enhanced electrical characteristics (frequency dispersion, hysteresis and interface trap density) than conventional thermal oxide and suppressed interfacial defect state. The decrease in defect state in conduction band edge and stress-induced leakage current (SILC) clearly indicate that plasma oxidation process improves SiO2 quality due to the reduced transition layer and energetically most stable interfacial state between SiO2/SiC controlled by the interstitial C.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.288-288
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• 2011

최근 Charge Trap Flash (CTF) Non-Volatile Memory (NVM) 소자가 30 nm node 이하로 보고 되면서, 고집적화 플래시 메모리 소자로 각광 받고 있다. 기존의 CTF NVM 소자의 tunnel layer로 쓰이는 SiO2는 성장의 용이성과 Si 기판과의 계면특성, 낮은 누설전류와 같은 장점을 지니고 있다. 하지만 단일층의 SiO2를 tunnel layer로 사용하는 기존의 Non-Valatile Memory (NVM)는 두께가 5 nm 이하에서 direct tunneling과 Stress Induced Leakage Current (SILC) 등의 효과로 인해 게이트 누설 전류가 증가하여 메모리 보존특성의 감소와 같은 신뢰성 저하에 문제점을 지니고 있다. 이를 극복하기 위한 방안으로, 최근 CTF NVM 소자의 Tunnel Barrier Engineered (TBE) 기술이 많이 접목되고 있는 상황이다. TBE 기술은 SiO2 단일층 대신에 서로 다른 유전율을 가지는 절연막을 적층시킴으로서 전계에 대한 민감도를 높여 메모리 소자의 쓰기/지우기 동작 특성과 보존특성을 동시에 개선하는 방법이다. 또한 터널링 절연막으로 유전률이 큰 High-K 물질을 이용하면 물리적인 두께를 증가시킴으로서 누설 전류를 줄이고, 단위 면적당 gate capacitance값을 늘릴 수 있어 메모리 소자의 동작 특성을 개선할 수 있다. 본 연구에서는 CTF NVM 소자의 trap layer로 쓰이는 HfO2의 두께를 5 nm, blocking layer의 역할을 하는 Al2O3의 두께를 12 nm로 하고, tunnel layer로 Si3N4막 위에 유전율과 Energy BandGap이 유사한 HfAlO와 ZrO2를 적층하여 Program/Erase Speed, Retention, Endurance를 측정을 통해 메모리 소자로서의 특성을 비교 분석하였다.