• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.173-174
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• 2007

In this paper, a new speed sensorless control based on an instantaneous reactive power and a fuzzy PI compensator are proposed for the interior permanent magnet synchronous motor (IPMSM) drives. The conventional fixed gain PI and PID controllers are very sensitive to step change of command speed, parameter variations and load disturbance. Also, to the estimated speeds are compensated by using an instantaneous reactive power in synchronously rotating reference frame. In a fuzzy compensator, the system control parameters are adjusted by a fuzzy rule based system, which is a logical model of the human behavior for process control. The effectiveness of algorithm is confirmed by the experiments.

• Proceedings of the KSR Conference
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• 2009.05b
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• pp.277-282
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• 2009

This research present final Proto-type design of Korean High speed EMU identity establishment. To making Proto-type design; Frist step is extracting design factor which can makes final image of Proto-type. And last, Apply it to the Original-form which was presented by last research. This research is for take one's own identity of korean High speed EMU, and makes originality of design for korean rail-road culture.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.3
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• pp.224-229
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• 2009

In this paper, an efficient signal interference control technique to improve the convergence speed of Adaptive transversal filter with LMS algorithm is introduced. The convergence characteristics of the proposed algorithm, whose coefficients are multiply adapted in a symbol time period by recycling the received data, are analyzed to prove theoretically the improvement of convergence speed. According as the step-size parameter ${\mu}$ is increased, the rate of convergence of the algorithm is controlled. Increasing the eigenvalue spread has the effect of controlling down the rate of convergence of the adaptive equalizer and also increasing the steady-state value of the average squared error and also demonstrate the superiority of signal interference control to the filter algorithm increasing convergence speed by (B+1) times due to the data-recycling LMS Algorithms.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.12
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• pp.1202-1209
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• 2004

This paper presents a design methodology of a Digital Servo Signal Processor for high speed CD-RW drive systems. The proposed Digital Servo Signal Processor enables us to develop CD-related systems for the very high speed applications and is one of the key components of the CD-RW systems. The proposed center compensation servo control is newly built for an actuator shaking due to the fast response of a step motor when it jumps to a long distance. A control method compensating for eccentricity of a disc is implemented for operating robustly at a higher rotational speed. This servo mechanism is more size efficient and less power consumed because it is implemented using a ARM7 embedded processor and hardware digital filters. Furthermore, it is convenient to upgrade firmware for the future required functions. From experimental results, we can see that the performance of the control system is improved greatly. The proposed servo algorithm shows a shorter setting time including a pull-in time and a faster access time. It can be applied easily to the DVD-ROM and the DVD-RAM which have the same optical structure.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.457-461
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• 2001

Advantages of switched reluctance motor(SRM) drives make it an attractive candidate for replacing adjustable speed ac and dc drives in both industrial and consumer applications. Furthermore, a simple, low cost and robust SRM drive can be efficiently operated in the hostile environment of an automobile. Generally, the speed control of SRM has a large step change or large torque reference, the output of its PI controller is often saturated. When this happens, the integral state is not consistent with the SRM input, while may give rise to the windup phenomenon. This paper proposes anti-windup control method for SRM speed control system by hysteresis current controlled asymmetry bridge converter. The experimental results show that the speed response has much improved performance, such as a small overshoot and fast settling time at the acceleration and particulary deceleration period with braking mode.

• Journal of the Korean Society for Precision Engineering
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• v.19 no.2
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• pp.203-212
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• 2002

Active magnetic hearings allow much high surface speed than conventional ball bearings and therefore greatly suitable for high speed cutting. This paper describes a design and test of an active magnetic bearing system with 16-pole radial magnets. The spindle is originally designed for a CNC lathe and driven by outer motor with 5.5 kW power and maximum speed 10,000 rpm. Considering static load condition and geometric restrictions, radial magnet is designed 16-pole type for smaller outer diameter of the spindle system. Dynamic system characteristics such as natural frequency, critical speed, stiffness, damping and system stabilities are simulated with a rigid rotor model including direct feedback controller. The designed spindle system is realized with digital PIDD controller to compensate phase lag of PWM amplifier and magnet coils. With levitation and step response experiment the control system characteristics are tested, and the spindle is rotated up to 10,000 rpm stab1y.

• The KSFM Journal of Fluid Machinery
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• v.14 no.5
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• pp.24-30
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• 2011

500W class MTG(Micro turbine generator) operating at 400,000 rpm is under development. From the cycle analysis, it is decided that the self-sustaining speed of MTG is 200,000rpm and the generating speed is 400,000 rpm. Therefore, motor should be designed so that it is able to rotate the rotor up to 200,000rpm and generator should designed so that it is able to generate 500W output at 400,000rpm. First step to design motor/generator is to determine the power and efficiency requirement. Not only the power into the compressor and from the turbine at the operating speed but also the mechanical and electrical losses should be considered in determining the power and efficiency requirement. This study presents the procedure and the results of determining the power and efficiency requirement considering the mechanical and electrical losses depending on the rotating speed which is measured from the experiment.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.365-368
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• 2001

This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It peformed the division and square-root by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.267-273
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• 2007

A fractional-N frequency synthesizer supports quadruple bands and multiple standards for mobile broadcasting systems. A novel linearized coarse tuned VCO adopting a pseudo-exponential capacitor bank structure is proposed to cover the wide bandwidth of 65%. The proposed technique successfully reduces the variations of KVCO and per-code frequency step by 3.2 and 2.7 times, respectively. For the divider and prescaler circuits, TSPC (true single-phase clock) logic is extensively utilized for high speed operation, low power consumption, and small silicon area. Implemented in $0.18-{\mu}m$ CMOS, the PLL covers $154{\sim}303$ MHz (VHF-III), $462{\sim}911$ MHz (UHF), and $1441{\sim}1887$ MHz (L1, L2) with two VCO's while dissipating 23 mA from 1.8 V supply. The integrated phase noise is 0.598 and 0.812 degree for the integer-N and fractional-N modes, respectively, at 750 MHz output frequency. The in-band noise at 10 kHz offset is -96 dBc/Hz for the integer-N mode and degraded only by 3 dB for the fractional-N mode.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.6
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• pp.104-110
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• 1994

We proposed a high speed feature extraction algorithm and developed a feature vector extraction chip for high speed character recognition. It is hard to implement a high speed OCR by software alone with statistical method . Thus, the whole recognition process is divided into functional steps, then pipeline processed so that high speed processing is possible with temporal parallelism of the steps. In this paper we discuss the feature extraction step of the functional steps. To extract feature vector, a character image is normalized to 40$\times$40 pixels. Then, it is divided into 5$\times$5 subregions and 4x4 subregions to construct 41 overlapped subregions(10x10 pixels). It requires to execute more than 500 commands to extract a feature vector of a subregion by software. The proposed algorithm, however, requires only 10 cycles since it can extract a feature vector of a columm of subregion in one cycle with array structure. Thus, it is possible to process 12.000 characters per second with the proposed algorithm. The chip is implemented using EPLD and the effectiveness is proved by developing an OCR using it.