• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.771-780
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• 2016

Detecting a set of longest paths is one of the crucial steps in static timing analysis and optimization. Recently, the process variation during manufacturing affects performance of the circuit design due to nanometer feature size. Measuring the performance of a circuit prior to its fabrication requires a considerable amount of computation time because it requires multi-corner and multi-mode analysis with process variations. An efficient algorithm of detecting the K-most critical paths in multi-corner multi-mode static timing analysis (MCMM STA) is proposed in this paper. The ISCAS'85 benchmark suite using a 32 nm technology is applied to verify the proposed method. The proposed K-most critical paths detection method reduces about 25% of computation time on average.

• The Transactions of the Korea Information Processing Society
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• v.4 no.6
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• pp.1481-1494
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• 1997

In hard real-time systems, a timing fault may yield catastrophic results. Dynamic scheduling provides the flexibility to compensate for unexpected events at runtime; however, scheduling overhead at runtime is relatively large, constraining both the accuracy of the timing and the complexity of the scheduling analysis. In contrast, static scheduling need not have any runtime overhead. Thus, it has the potential to guarantee the precise time at which each instruction implementing a control action will execute. This paper presents a new approach to the problem of analyzing high-level language code, augmented by arbitrary before and after timing constraints, to provide a valid static schedule. Our technique is based on instruction-level complier code scheduling and timing analysis, and can ensure the timing of control operations to within a single instruction clock cycle. Because the search space for a valid static schedule is very large, a novel adaptive genetic search algorithm was developed.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.357-360
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• 2002

In this paper, we propose a technique to eliminate 1,he effect of false paths in the calculation of the distribution of the maximum delay of a given CMOS combinatorial circuit, when distributions of interconnect delays and gate switching delays of the circuit are given. The technique can be incorporated into our algorithm for the statistical static timing analysis, which can take correlations of the delays into account.

• Journal of Communications and Networks
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• v.6 no.2
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• pp.182-191
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• 2004

In this paper, performances of different ultra-wideband (UWB) modulation schemes in the presence of timing jitter are evaluated and compared. Static and Rayleigh fading channels are considered. For fading channels, Oat and dispersive channels are assumed. First, bit error rate (BER) performances for each case are derived for a fixed value of timing jitter. Later, a uniform distribution of jitter is assumed to evaluate the performance of the system, and the theoretical results are verified by computer simulations. Finger estimation error is treated as timing jitter and an appropriate model is generated. Furthermore, a worst case distribution that provides an upper bound on the system performance is presented and compared with other distributions. Effects of timing jitter on systems employing different pulse shapes are analyzed to show the dependency of UWB performance on pulse shape. Although our analysis assumes uniform timing jitter, our framework can be used to evaluate the BER performance for any given probability distribution function of the jitter.

• Journal of the Korea Society of Computer and Information
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• v.15 no.4
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• pp.37-45
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• 2010

A system which needs timely accuracy has to design and to verify correctly about execution-time for reliability. Accordingly, it is necessary for timing analysis tools, and much previous research worked. In timing analysis tool, there are two methods. One is a static analysis, and the other is a measurement based analysis. A static analysis is able to spend time less than a measurement based analysis method, but has low reliability of analysis result caused by hard to estimate time of I/O caused by various hardware. A measurement based analysis can be close analysis to real result, but it is hard to adapt to actual application, and spend a lot of time to get result of analysis. As such, this paper present a software monitoring architecture to supply reliability of static analysis process. In a presented architecture, it can select target as needed measurement through static analysis, and reuse result of measurement exist. Therefore, The architecture can reduce overload of time and performance for measurement, and improve the reliability which is the worst problem of static analysis.

• Journal of Electrical Engineering and information Science
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• v.1 no.1
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• pp.118-128
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• 1996

In safety critical hard real-time systems, a timing fault may yield catastrophic results. In order to eliminate the timing faults from the fast responsive real-time control systems, it is necessary to schedule a code based on high precision timing analysis. Further, the schedulability enhancement by having multiple processors is of wide spread interest. However, although an instruction level parallel processing is quite effective to improve the schedulability of such a system, none of the real-time applications employ instruction level parallel scheduling techniques because most of the real-time scheduling models have not been designed for fine-grain execution. In this paper, we present a timing constraint model specifying high precision timing constraints, and a practical approach for constructing static schedules for a VLIW execution model. The new model and analysis can guarantee timing accuracy to within a single machine clock cycle.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.391-393
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• 2004

For performance and stability of a synchronized system, we need an efficient Clock Tree Synthesis(CTS) methodology to design clock distribution networks. In a system-on-a-chip(SOC) design environment, CTS effectively distributes clock signals from clock sources to synchronized points on layout design. In this paper, we suggest the pre-layout analysis of the clock network including gated clock, multiple clock, and test mode CTS optimization. This analysis can help to avoid design failure with potential CTS problems from logic designers and supply layout constraints so as to get an optimal clock distribution network. Our new design flow including pre-layout CTS analysis and structural violation checking also contributes to reduce design time significantly.

• Journal of Positioning, Navigation, and Timing
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• v.5 no.1
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• pp.21-28
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• 2016

The Wide Area Differential Global Positioning System (WADGPS) that uses a number of Global Navigation Satellite System (GNSS) reference stations are implemented with various types and provide services as it can service a wide range of areas relatively. This paper discusses a constellation design of reference stations and performance analysis of the WADGPS. It presented performance results of static and dynamic users when wide area correction algorithm was applied using eight reference stations.

• Journal of Computing Science and Engineering
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• v.6 no.4
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• pp.267-278
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• 2012

The state-of-the-art techniques in multicore timing analysis are limited to analyze multicores with shared instruction caches only. This paper proposes a uniform framework to analyze the worst-case performance for both shared instruction caches and data caches in a multicore platform. Our approach is based on a new concept called address flow graph, which can be used to model both instruction and data accesses for timing analysis. Our experiments, as a proof-of-concept study, indicate that the proposed approach can accurately compute the worst-case performance for real-time threads running on a dual-core processor with a shared L2 cache (either to store instructions or data).

• ETRI Journal
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• v.38 no.3
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• pp.479-486
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• 2016

System-on-chip (SoC) designs have a number of flip-flops; the more flip-flops an SoC has, the longer the associated scan test application time will be. A scan shift operation accounts for a significant portion of a scan test application time. This paper presents physical-aware approaches for speeding up scan shift operations in SoCs. To improve the speed of a scan shift operation, we propose a layout-aware flip-flop insertion and scan shift operation-aware physical implementation procedure. The proposed combined method of insertion and procedure effectively improves the speed of a scan shift operation. Static timing analyses of state-of-the-art SoC designs show that the proposed approaches help increase the speeds of scan shift operations by up to 4.1 times that reached under a conventional method. The faster scan shift operation speeds help to shorten scan test application times, thus reducing test costs.