• Title/Summary/Keyword: speed data

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A Study on the Wind Data Analysis and Wind Speed Forecasting in Jeju Area (제주지역 바람자료 분석 및 풍속 예측에 관한 연구)

  • Park, Yun-Ho;Kim, Kyung-Bo;Her, Soo-Young;Lee, Young-Mi;Huh, Jong-Chul
    • Journal of the Korean Solar Energy Society
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    • v.30 no.6
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    • pp.66-72
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    • 2010
  • In this study, we analyzed the characteristics of wind speed and wind direction at different locations in Jeju area using past 10 years observed data and used them in our wind power forecasting model. Generally the strongest hourly wind speeds were observed during daytime(13KST~15KST) whilst the strongest monthly wind speeds were measured during January and February. The analysis with regards to the available wind speeds for power generation gave percentages of 83%, 67%, 65% and 59% of wind speeds over 4m/s for the locations Gosan, Sungsan, Jeju site and Seogwipo site, respectively. Consequently the most favorable periods for power generation in Jeju area are in the winter season and generally during daytime. The predicted wind speed from the forecast model was in average lower(0.7m/s) than the observed wind speed and the correlation coefficient was decreasing with longer prediction times(0.84 for 1h, 0.77 for 12h, 0.72 for 24h and 0.67 for 48h). For the 12hour prediction horizon prediction errors were about 22~23%, increased gradually up to 25~29% for 48 hours predictions.

A Study on Binary CDMA System Correlator Design for High-Speed Acquisition Processing (고속 동기 처리를 위한 Binary CDMA 시스템 코릴레이터 설계에 관한 연구)

  • Lee, Seon-Keun;Jeong, Woo-Yeol
    • Journal of the Korea Society of Computer and Information
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    • v.12 no.1 s.45
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    • pp.155-160
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    • 2007
  • Because output of multi-code CDMA system adapted high speed data transmission becoming multi-level system use linear amplifier in output stage and complex output signal. Therefore, Multi-Code CDMA system has shortcoming of high price, high complexity etc.. Binary CDMA technology that allow fetters in existing CDMA technology to supplement this shortcoming proposed. In binary CDMA system When correlator process high speed data, bottle-neck phenomenon is happened on synchronization acquisition process, it is very important parameter. Because existent correlator must there be advantage that power consumption is small but flow addition of several stages to receive correlation's value, the processing speed has disadvantage because the operation amount is much. Therefore in this paper, proposed correlator has characteristic such as data is able to high speed processing, chip area is independent and power consumption is constant in structure in binary CDMA system.

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A Design of Correlator with the PBS Architecture in Binary CDMA System (Binary CDMA 시스템에서 PBS 구조를 가지는 코릴레이터 설계)

  • Lee, Seon-Keun;Jeong, Woo-Yeol
    • The Journal of the Korea institute of electronic communication sciences
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    • v.3 no.3
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    • pp.177-182
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    • 2008
  • Because output of multi-code CDMA system adapted high speed data transmission becoming multi-level system use linear amplifier in output stage and complex output signal. Therefore, Multi-Code CDMA system has shortcoming of high price, high complexity etc. Binary CDMA technology that allow fetters in existing CDMA technology to supplement this shortcoming proposed. In binary CDMA system When correlator process high speed data, bottle-neck phenomenon is happened on synchronization acquisition process, it is very important parameter. Because existent correlator must there be advantage that power consumption is small but flow addition of several stages to receive correlation's value, the processing speed has disadvantage because the operation amount is much. Therefore in this paper, proposed correlator has characteristic such as data is able to high speed processing, chip area is independent and power consumption is constant in structure in binary CDMA system.

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A 200MHz high speed 16M SDRAM with negative delay circuit (부지연 회로를 내장한 200MHz 고속 16M SDRAM)

  • 김창선;장성진;김태훈;이재구;박진석;정웅식;전영현
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.34C no.4
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    • pp.16-25
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    • 1997
  • This paper shows a SDRAM opeating in 200MHz clock cycle which it use data interleave and pipelining for high speed operation. We proposed NdC (Negative DEaly circuit) to improve clock to access time(tAC) characteristics, also we proposed low power WL(wordline)driver circit and high efficiency VPP charge-pump circit. Our all circuits has been fabricated using 0.4um CMOS process, and the measured maximum speed is 200Mbytes/s in LvTTL interface.

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High Speed Controller for Haptic System (촉각장치 구동용 고속제어기)

  • 김동옥
    • Proceedings of the KIPE Conference
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    • 2000.07a
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    • pp.61-65
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    • 2000
  • In this paper We have developed the high-speed controller for haptic control. The proposed controller is based on the PCI/FPGA technology which can calculate the real position and transmit the force data to device rapidly. The haptic system is composed of 6DOF force display device high-speed controller. The developed system will be used on constructing the dynamical virtual environment. To show the efficiency of our system we designed simulation program of force-reflecting. As the result of the experiment we found that the controller has much higher resolution than some other controller It is so efficient in a 1 PC-based system with 1[kHz] haptic interrupt cycle.

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Diagnosis of Excessive Vibration Signals of Two-Pole Generator Rotors in Balancing

  • Park, Jong-Po
    • Journal of Mechanical Science and Technology
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    • v.14 no.6
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    • pp.590-596
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    • 2000
  • Cause of excessive vibration with twice the rotational speed of a two-pole generator rotor for the fossil power plants was investigated. The two-pole generator rotor, treated as a typically asymmetric rotor in vibration analysis, produces asynchronous vibration with twice the rotational speed, sub-harmonic critical speeds, and potentially unstable operating zones due to its own inertia and/or stiffness asymmetry. This paper introduces a practical balancing procedure, and presents the results of the investigation on sources of the excessive vibration based on the experimental vibration data of the asymmetric two-pole rotor in balancing.

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The Variation of $SO_2$ Concentration According to Wind Speed in Urban Area (도심지역에서의 풍속에 따른 $SO_2$ 농도변화)

  • 羅振均
    • Journal of Korean Society for Atmospheric Environment
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    • v.5 no.2
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    • pp.97-105
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    • 1989
  • Recently, many studies on air quality prediction models have been performed to develope new ones. The purpose of the study is to obtain a method to predict $SO_2$ concentration simply in urban area using hour-to-hour meteorological data such as the wind speed, the incoming solar radiation, and the cloud coverages. The relationships between with speed and $SO_2$ concentrations are plotted in flgures. Predicted concentration curves are obtained for equation C=b/(1+au).

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Design Techniques of Tilting Train(TTX) using the system engineering (PDM) (SE관리기법(PDM)을 이용한 틸팅차량(TTX) 설계기술 연구)

  • Han Seong-ho;Song Yong-su
    • Proceedings of the Korean Society For Composite Materials Conference
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    • 2004.10a
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    • pp.203-206
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    • 2004
  • Tilting train has been developed to increase the operational speed of the trains on conventional lines which have many curves. This train are tilted at curves to compensate for unbalanced carbody centrifugal acceleration to a greater extent than compensation produced by the track cant, so that passengers do not feel centrifugal acceleration and thus trains can run at higher speed at curves. This paper developed PDM(product data managemnet) to make a system engineering of TTX(tilting train express) with maximum operation speed 180 km/h.

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Design of Interface Bridge in IP-based SOC

  • 정휘성;양훈모;이문기
    • Proceedings of the IEEK Conference
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    • 2001.06b
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    • pp.349-352
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    • 2001
  • As microprocessor and SOC (System On a Chip) performance moves into the GHz speed, the high-speed asynchronous design is becoming challenge due to the disadvantageous power and speed aspects in synchronous designs. The next generation on-chip systems will consist of multiple independently synchronous modules and asynchronous modules for higher performance, so the interface module for data transfer between multiple clocked IPs is designed with Xilinx FPGA and simulated with RISC microprocessor.

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Train Performance Simulation for Korea High Speed Train (한국형 고속전철 개발차량 열차성능 해석)

  • 이태형;박춘수;목진용
    • Proceedings of the KSR Conference
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    • 2003.10a
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    • pp.199-203
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    • 2003
  • Computer aided simulation is becoming an essential part in planning, design, and operation of railway systems. To determine the adequate performance and specification of railway system, it is necessary to calculate rotting stock's performance such as distance, speed, power etc when train's running. This paper presents result of train performance simulation using the program that developed in advance for Korea high speed train. To verify result of simulation, we have compared that with experiment data.

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