• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.7-11
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• 2017

In this paper, we have studied the characteristics of NAND Flash memory in SONOS Poly-Si Thin Film Transistor (Poly-Si TFT) device. Source/drain junctions(S/D) of cells were not implanted and selective transistors were located in the end of cells. We found the optimum conditions of process by means of the estimation for the doping concentration of channel and source/drain of selective transistor. As the doping concentration was increased, the channel current was increased and the characteristic of erase was improved. It was believed that the improvement of erase characteristic was probably due to the higher channel potential induced by GIDL current at the abrupt junction. In the condition of process optimum, program windows of threshold voltages were about 2.5V after writing and erasing. In addition, it was obtained that the swing value of poly Si TFT and the reliability by bake were enhanced by increasing process temperature of tunnel oxide.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.352.1-352.1
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• 2014

Indium Tin Oxide (ITO) films are the most extensively studied and commonly used as ones of TCO films. The ITO films having a high electric conductivity and high transparency are easily fabricated on glass substrate at a substrate temperature over $250^{\circ}C$. However, glass substrates are somewhat heavy and brittle, whereas plastic substrates are lightweight, unbreakable, and so on. For these reasons, it has been recently suggested to use plastic substrates for flexible display application instead of glass. Many reaearchers have tried to produce high quality thin films at rood temperatures by using several methods. Therefore, amorphous ITO films excluding thermal process exhibit a decrease in electrical conductivity and optical transparency with time and a very poor chemical stability. However the amorphous Indium Gallium Zinc Oxide (IGZO) offers several advantages. For typical instance, unlike either crystalline or amorphous ITO, same and higher than a-IGZO resistivity is found when no reactive oxygen is added to the sputter chamber, this greatly simplifies the deposition. We reported on the characteristics of a-IGZO thin films were fabricated by RF-magnetron sputtering method on the PEN substrate at room temperature using 3inch sputtering targets different rate of Zn. The homogeneous and stable targets were prepared by calcine and sintering process. Furthermore, two types of IGZO TFT design, a- IGZO source/drain material in TFT and the other a- ITO source/drain material, have been fabricated for comparison with each other. The experimental results reveal that the a- IGZO source/drain electrode in IGZO TFT is shown to be superior TFT performances, compared with a- ITO source/drain electrode in IGZO TFT.

• Advances in nano research
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• v.15 no.3
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• pp.263-275
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• 2023

The electron transport properties of Y-type zigzag branched carbon nanotubes (CNTs) are of great significance for micro and nano carbon-based electronic devices and their interconnection. Based on the semi-empirical method combining tight-binding density functional theory and non-equilibrium Green's function, the electron transport properties between the branches of Y-type zigzag branched CNT are studied. The results show that the drain-source current of semiconducting Y-type zigzag branched CNT (8, 0)-(4, 0)-(4, 0) is cut-off and not affected by the gate voltage in a bias voltage range [-0.5 V, 0.5 V]. The current presents a nonlinear change in a bias voltage range [-1.5 V, -0.5 V] and [0.5 V, 1.5 V]. The tangent slope of the current-voltage curve can be changed by the gate voltage to realize the regulation of the current. The regulation effect under negative bias voltage is more significant. For the larger diameter semiconducting Y-type zigzag branched CNT (10, 0)-(5, 0)-(5, 0), only the value of drain-source current increases due to the larger diameter. For metallic Y-type zigzag branched CNT (12, 0)-(6, 0)-(6, 0), the drain-source current presents a linear change in a bias voltage range [-1.5 V, 1.5 V] and is symmetrical about (0, 0). The slope of current-voltage line can be changed by the gate voltage to realize the regulation of the current. For three kinds of Y-type zigzag branched CNT with different diameters and different conductivity, the current-voltage curve trend changes from decline to rise when the branch of drain-source is exchanged. The current regulation effect of semiconducting Y-type zigzag branched CNT under negative bias voltage is also more significant.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.3
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• pp.196-208
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• 2007

An analytical model is proposed for an optically controlled Metal Semiconductor Field Effect Transistor (MESFET), known as Optical Field Effect Transistor (OPFET) considering the diffusion fabrication process. The electrical parameters such as threshold voltage, drain-source current, gate capacitances and switching response have been determined for the dark and various illuminated conditions. The Photovoltaic effect due to photogenerated carriers under illumination is shown to modulate the channel cross-section, which in turn significantly changes the threshold voltage, drainsource current, the gate capacitances and the device switching speed. The threshold voltage $V_T$ is reduced under optical illumination condition, which leads the device to change the device property from enhancement mode to depletion mode depending on photon impurity flux density. The resulting I-V characteristics show that the drain-source current IDS for different gate-source voltage $V_{gs}$ is significantly increased with optical illumination for photon flux densities of ${\Phi}=10^{15}\;and\;10^{17}/cm^2s$ compared to the dark condition. Further more, the drain-source current as a function of drain-source voltage $V_{DS}$ is evaluated to find the I-V characteristics for various pinch-off voltages $V_P$ for optimization of impurity flux density $Q_{Diff}$ by diffusion process. The resulting I-V characteristics also show that the diffusion process introduces less process-induced damage compared to ion implantation, which suffers from current reduction due to a large number of defects introduced by the ion implantation process. Further the results show significant increase in gate-source capacitance $C_{gs}$ and gate-drain capacitance $C_{gd}$ for optical illuminations, where the photo-induced voltage has a significant role on gate capacitances. The switching time ${\tau}$ of the OPFET device is computed for dark and illumination conditions. The switching time ${\tau}$ is greatly reduced by optical illumination and is also a function of device active layer thickness and corresponding impurity flux density $Q_{Diff}$. Thus it is shown that the diffusion process shows great potential for improvement of optoelectronic devices in quantum efficiency and other performance areas.

• Proceedings of the KSR Conference
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• 1999.11a
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• pp.407-414
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• 1999

Sand drain as a vertical drainage is widely used in soft ground improvement. Recently, sand, the principal source of sand drain, is running out. A laboratory model test was carried out to utilize gravel as a substitute for sand. Though which the characteristics of gravel are compared to those of sand for engineering purpose. According to the test, the settlement was found to be smaller in gravel drain than in sand drain. The increase in bearing capacity by gravel rile explains the result. The clogging effect was not found in gravel column. As a result, it is assumed that gravel is relatively acceptable as a drainage material. Gravel material seems better than sand material in bearing capacity and it is found that bearing capacity is larger when gravel is used as compaction pile than as drain from in-situ test on bearing capacity. Increase of bearing capacity with gravel pile means an effect of composite ground by stiffness of gravel material. It can lie supposed to use gravel pile instead of sand pile in view of consolidation effect and bearing capacity.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.62-66
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• 2011

In this study, a new RF method to extract the drain-source voltage Vds-dependent gate-bulk capacitance of deep-submicron MOSFETs is developed by determining Vds-independent gate-source overlap capacitance using measured S-parameters. The accuracy of extraction method is verified by observing good agreements between the measured and modeled S-parameters. The lateral channel doping profile in the drain region is experimentally measured using a Vds-dependent curve of the overlap and depletion length obtained from the extracted data.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.1277-1280
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• 2005

A high-aspect-ratio and high-resolution stainless steel shadow mask for organic thin-film transistors (OTFTs) circuit has been fabricated by a new method which combines photochemical machining, micro-electrical discharge machining (micro-EDM), and electrochemical etching (ECE). First, connection lines and source-drain holes are roughly machined by photochemical etching, and then the part of source and drain holes is finished by the combination of micro-EDM and ECE processes. Using this method a $100\;\mu{m}$ thick stainless steel (AISI 304) shadow mask for inverter can be fabricated with the channel length of $30\;\mu{m}\;and\;10\;\mu{m}\;respectively.\;The\;width\;of\;connection line\;is\;150\;\mu{m}$. The aspect ratio of the wall is about 5 and 15, respectively. Metal lines and source-drain electrodes of OTFTs were successfully deposited through the fabricated shadow mask.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2009.04a
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• pp.194-202
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• 2009

The paper deals with the countermeasure against structure-borne noise source and noise reduction of drainage pipes. Recently, the problem the problem of the toilet drain noise of an apartment house has been become the center of public interest and a target of public grievance. Generally, the drain noise of a toilet in the apartment house has a pink noise characteristics below 2 kHz level, and therefore, the structure-borne noise has a great effect on the entire drain noise. In order to measure the transmission loss for various kinds of pipes such as PVC pipes, cast-iron pipes and newly developed AS pipes, experimental setup containing speakers as a sound source was designed and manufactured. The second-stories measurement room with a small size anechoic chamber was constructed and the noise level for different kinds of drainage pipes was measured by the sound level meter. Through the experimental research in the study, noise reduction capacity for various kinds of drainage pipes and countermeasures against structure-borne noise source are demonstrated.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.54-57
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• 2002

In this study, a new programming method, to minimize the generation of Si-SiO$_2$ interface traps of scaled SONOS flash memory as a function of number of program/erase cycles has been proposed. In the proposed programming method, power supply voltage is applied to the gate, forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim (MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and drain are open. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ prograss/erase cycles can be realized by the proposed programming method. The asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics of scaled SONOS devices because electrical stress applied to the Si-SiO$_2$ interface is reduced by short programming time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1001-1007
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• 2002

In this paper we analyzed the effects of pentacene thickness and the location of source/drain contacts on the performance of pentacene TFT Above a certain thickness of pentacene thin film the pentacene grain was turned from the thin film phase into the bulk phase, resulting in degrading the crystallinity and then performance as well. For the top contact structure in which source/drain contacts are located above pentacene film, the contact resistance decreased comparing with the bottom contact structure. However, the leakage current in the off-state became large and then the related parameters such as on/off current ratio were deteriorated. We found that the thickness of around 300$\AA$-700$\AA$ was suitable, and that the bottom contact was more feasible for hig Performance pentacene OTFT.