• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.155-158
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• 2007

Printed organic thin-film transistor(OTFT) to use as a switching device for an organic light emitting diode(OLED) were fabricated in the microcontact printing and direct printing processes at room temperature. The gate electrodes($5{\mu}m$, $10{\mu}m$, and $20{\mu}m$) of OTFT was fabricated using microcontact printing process, and source/drain electrodes ($W/L=500{\mu}m/5{\mu}m$, $500{\mu}m/10{\mu}m$, and $500{\mu}m/20{\mu}m$) was fabricated using direct printing process with hard poly(dimethylsiloxane)(h-PDMS) stamp. Printed OTFT with dielectric layer was formed using special coating system and organic semiconductor layer was ink-jet printing process. Microcontact printing and direct printing processes using h-PDMS stamp made it possible to fabricate printed OTFT with channel lengths down to $5{\mu}m$, and reduced the process by 20 steps compared with photolithography. As results of measuring he transfer characteristics and output characteristics of OTFT fabricated with the printing process, the field effect characteristic was verified.

• Journal of Electrical Engineering and information Science
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• 제2권6호
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• pp.202-207
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• 1997

Design and fabrication issues for an L-band GaAs Monolithic Microwave Integrated Circuit(MMIC) Voltage Controlled Oscillator(VCO) as a component of Personal Communications Systems(PCS) Radio Frequency(RF) transceiver are discussed. An ion-implanted GaAs MESFET tailored toward low current and low noise with 0.5mm gate length and 300mm gate width has been used as an active device, while an FET with the drain shorted to the source has been used as the voltage variable capacitor. The principal design was based on a self-biased FET with capacitive feedback. A tuning range of 140MHz and 58MHz has been obtained by 3V change for a 600mm and a 300mm devices, respectively. The oscillator output power was 6.5dBm wth 14mA DC current supply at 3.6V. The phase noise without any buffer or PLL was 93dB/1Hz at 100KHz offset. Harmonic balance analysis was used for the non-linear simulation after a linear simulation. All layout induced parasitics were incorporated into the simulation with EEFET2 non-linear FET model. The fabricated circuits were measured using a coplanar-type probe for bare chips and test jigs with ceramic packages.

• Transactions on Electrical and Electronic Materials
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• 제10권6호
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• pp.193-195
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• 2009

This paper aims to develop a low gate source voltage ($V_{gs}$) N-LDMOS element that is fully operational at a CMOS Logic Gate voltage (3.3 or 5 V) realized using the 0.35 μm BCDMOS process. The basic structure of the N-LDMOS element presented here has a Low $V_{gs}$ LDMOS structure to which the thickness of a logic gate oxide is applied. Additional modification has been carried out in order to obtain features of an improved breakdown voltage and a specific on resistance ($R_{sp}$). A N-LDMOS element can be developed with improved features of breakdown voltage and specific on resistance, which is an important criterion for power elements by means of using a proper structure and appropriate process modification. In this paper, the structure has been made to withstand the excessive electrical field on the drain side by applying the double gate oxide structure to the channel area, to improve the specific on resistance in addition to providing a sufficient breakdown voltage margin. It is shown that the resulting modified N-LDMOS structure with the feature of the specific on resistance is improved by 31%, and so it is expected that optimized power efficiencies and the size-effectiveness can be obtained.

• 한국전기전자재료학회논문지
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• 제20권12호
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• pp.1056-1061
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• 2007

A sublimation epitaxial method, referred to as the Closed Space Technique (CST) was adopted to produce thick SiC epitaxial layers for power device applications. In this study, we aimed to systematically investigate surface morphologies and electrical properties of SiC epitaxial layers grown with varying a SiC/Al ratio in a SiC source powder during the sublimation growth using the CST method. The surface morphology was dramatically changed with varying the SiC/Al ratio. When the SiC/Al ratio of 90/1 was used, the step bunching was not observed in this magnification and the ratio of SiC/Al is an optimized range to grow of p-type SiC epitaxial layer. It was confirmed that the acceptor concentration of epitaxial layer was continuously decreased with increasing the SiC/Al ratio. 4H-SiC MESFETs haying a micron-gate length were fabricated using a lithography process and their current-voltage performances were characterized. It was confirmed that the increase of the negative voltage applied on the gate reduced the drain current, showing normal operation of FET device.

• 대한전자공학회논문지SD
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• 제40권11호
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• pp.1-8
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• 2003

본 논문에서는 소스/드레인 및 게이트의 불순물에 따른 실리사이드의 의존성을 면저항과 단면 특성 등의 분석을 통하여 연구하였다. 급속 열처리 후에는 As, P, BF₂, B/sub 11/ 등과 같은 불순물에 대한 먼저항의 차이가 거의 나지 않았다. 하지만 실리사이드 형성 후히 고온 열처리시에 그 특성이 매우 크게 변화하였다. BF₂를 주입한 시편에서의 특성이 가장 좋게 나타난 반면, As를 주입한 실리사이드의 특성이 가장 열화되었다. BF₂를 주입한 시편에서의 실리사이드 특성 향상은 flourine에 의한 니켈의 확산 방지 때문인 것으로 여겨진다. 그러므로 실리사이드의 성능 향상을 위해 Ni의 확산을 방지시키는 것이 매우 필요하다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -2
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• pp.1009-1012
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• 2000

In this paper, we have designed and fabricated power PHEMT’s with an unit gate width of 80$\mu\textrm{m}$ and 4 fingers, and MIMIC power amplifiers using the PHEMT’s as well. The PHEMT’s have a 0.2$\mu\textrm{m}$ gate length and source to drain spacing of 3$\mu\textrm{m}$. The characteristics of the fabricated PHEMT’s are 4.08dB of S$\sub$21/ gain at the 35GHz and 317mS/mm of gm, and 62GHz of f$\sub$T/ and 120GHz of f$\sub$max/. The designed and fabricated MIMIC’s power amplifiers with 6 PHEMT’s and MIN capacitors were fully passivated by 1000 Α of Si$_3$N$_4$ film for higher performance and surface protects. The chips were processed using the MINT processes, and size was 3.25 ${\times}$ 1.8$\textrm{mm}^2$. The fabricated MIMIC power amplifiers have RF characteristics such as 11.25dB of S$\sub$21/ gain, 11.37dB of input return-loss and 12.69dB of output return-loss at the 34.55GHz.

• 한국통신학회논문지
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• 제36권10A호
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• pp.847-851
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• 2011

본 논문에서는 밀리미터파 응용에서 사용 가능한 우수한 성능의 MMIC (Millimeter-wave Monolithic Integrated Circuit) star 혼합기를 구현하였다. MMIC star 혼합기를 구현하기 위하여 PHEMT (pseudomorphic high electron mobility transistor) 공정 기반의 소오스와 드레인 단자를 연결한 쇼트키 (Schottky) 다이오드를 사용하였다. 혼합기의 측정 결과 LO 주파수가 75 GHz이며 전력이 10 dBm 인 경우, 81 GHz에서 86 GHz의 RF 주파수 범위에서 평균 13 dB의 변환손실 특성을 얻었다. RF-LO 격리도 특성은 30 dB 이상의 결과를 얻었으며 약 4 dBm의 P1 dB 특성을 얻었다. 전체 칩의 크기는 0.8 mm ${\times}$ 0.8 mm이다.

• 한국전기전자재료학회논문지
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• 제20권6호
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• pp.487-490
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• 2007

In this paper, the formation and thermal stability characteristics of Ni silicide using Ni-V alloy on Boron cluster ($B_{18}H_{22}$) implanted bulk and SOI substrate were examined in comparison with pure Ni for nano-scale CMOSFET. The Ni silicide using Ni-V alloy on $B_{18}H_{22}$ implanted SOI substrate after high temperature post-silicidation annealing showed the lower sheet resistance, no agglomeration interface image and lower surface roughness than that using pure Ni. The thermal stability of Ni silicide was improved by using Ni-V alloy on $B_{18}H_{22}$ implanted SOI substrate.

• 전력전자학회논문지
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• 제11권4호
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• pp.361-370
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• 2006

단일단 단일스위치 통기정류기형 플라이백 컨버터를 제안한다. 제안된 단일단 단일스위치에 의해 역률이 개선되었으며 IEC 61000-3-2의 고조파 전류 요구조건을 만족한다. Flyback 컨버터의 경우 2 차 측 정류용 다이오드로 사용되는 쇼트키 다이오드의 전압 강하에 의한 전력손실이 크며, 이러한 전력 손실을 줄이기 위해 정류용 다이오드를 대신하여 도통 저항이 작은 MOSFET을 사용함으로써 전력손실을 줄일 수 있으며 이를 동기정류기 (SR : Synchronous Rectifier)라 한다. 제안된 동기 정류기는 MOSFET의 드레인 소스간의 전압 강하를 이용하여 동작하는 VDSR(Voltage Driven Synchronous Rectifier)이며 효율 향상을 목적으로 한다. 본 논문에서 제안한 단일단 단일스위치 동기정류기형 플라이백 컨버터는 출력 전력 85W (l2V /7.1A)에 적용되었으며 실험결과를 통해 확인할 수 있다.

• 조명전기설비학회논문지
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• 제27권3호
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• pp.55-64
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• 2013

In this paper, a new topology which can add a small reactor in series to a condenser-bank type reactive power compensator to limit current is proposed. And also the proposed topology can add or remove a power condenser safely without any addition of inrush-current suppression resistance. The proposed method tests variable resistance of the drain source of a switching device which is controlled by gate voltage in a two-way switch with a diode rectifier and FET switch. In other words, the proposed method is a inrush-current suppression method with the structure of variable resistance. In particular, the proposed method creates smooth current without any resonance in inrush-current as well as is not limited by the time of switch on and off.