• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.191-191
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• 2010

차세대 디스플레이를 위한 소자로 활용 가능한 Oxide Semiconductor TFT를 bottom gate 타입의 TFT 소자를 제작하였다. 투명 박막 트랜지스터 제작과 관련해서 ITO가 증착된 glass 기판을 gate 전극으로 사용하였고, 게이트 dielectric으로 $SiO_2/Si_3N_4$를 PECVD 방법을 사용해 증착하였으며, 채널 영역으로 ZnO를 RF magnetron sputtering을 이용하여 RF power 및 공정 압력에 따른 구조적, 광학적, 전기적 특성을 조사하였다. ZnO 박막의 공정 변수로 RF파워는 25W, 50W, 75W, 100W로 변화시키고, 증착 압력은 20m, 100m, 200m 300mTorr로 변화시켰다. Source/Drain 사이에 채널 형성 및 게이트 dielectric에서 누설전류가 TFT 특성에 미치는 영향을 연구하였다. ZnO 박막은 증착 파워 및 공정 압력에 따라 박막의 결정성이 현저하게 변화하는 것을 알 수 있었으며, 그러한 박막의 미세구조 가 TFT의 전기적인 특성에 크게 영향을 미치는 것으로 판단된다

• 전력전자학회:학술대회논문집
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• 전력전자학회 2015년도 추계학술대회 논문집
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• pp.85-86
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• 2015

In this paper, the bidirectional DC-DC converter is composed of the 900V Silicon-Carbide(SiC) devices to get high efficiency. The 900V SiC device is better than a similar current rated traditional SiC device. it has a lower drain-source resistance and output capacitance. therefore it can reduce the switching and the conduction losses of the DC-DC converter. The experimental results verify the improvement of efficiency and usefulness of 900V SiC device.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2008년도 추계학술대회 논문집
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• pp.400-405
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• 2008

Motor is energy converting system to generate mechanical force from electrical power and there are various typed motors in home, office, factory, vehicles, aircraft, shipping, etc. Recently in compliance with performance and reliability and the applications of variable speed motors with invert driver are expanded. Almost high power inverter have IGBT and IGBT's fault cause motor system fault. If we can calculate and foresee troubles of IGBT, we can protect accident caused by motor system fault. In this paper, the deterioration test method of IGBT devices is proposed and the test results of proposed method are shown by evaluated equipment. The basic concept of proposed method is current-voltage characteristic curve test between drain and source of IGBT in open state. The applied voltage type is ramp and it is confirmed that the current-voltage curvet pattern of IGBT in open state represents IGBT's deterioration state.

• 반도체디스플레이기술학회지
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• 제20권2호
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• pp.82-86
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• 2021

In this study, we investigated the oxygen partial pressure effect of ITO films for electrodes of oxide-based Thin-Film Transistor (TFT). Firstly, we deposited single ITO films on the glass substrate at room temperature. ITO films were prepared at the various partial pressures of oxygen gas 0-7.4% (O₂/(Ar+O₂)). As increasing oxygen on the process of film deposition, electrical properties were improved and optical transmittance increased in the visible light range (300-800 nm). For the electrode of TFT, we fabricated a TFT device (W/L=1000/200 ㎛) with ITO films as the source and drain electrode on the silicon wafer. Except for the TFT device combined with ITO film prepared at the oxygen partial pressure ratio of 7.4%, We confirmed that TFT devices with ITO films via FTS system operated as a driving device at threshold voltage (V_th) of 4V.

• ETRI Journal
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• 제44권3호
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• pp.504-511
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• 2022

Monte Carlo simulations show that, as temperature increases, the average kinetic energy of channel electrons in a GaN transistor first decreases and then increases. According to the calculations, the relative energy change reaches 40%. This change leads to a reduced barrier height due to quantum coupling among the three-dimensional motions of channel electrons. Thus, an analysis and physical model of the gate leakage current that includes drift velocity is proposed. Numerical calculations show that the negative and positive temperature dependence of gate leakage currents decreases across the barrier as the field increases. They also demonstrate that source-drain voltage can have an effect of 1 to 2 orders of magnitude on the gate leakage current. The proposed model agrees well with the experimental results.

• 한국농공학회지
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• 제45권7호
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• pp.57-69
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• 2003

To evaluate nutrient dynamics with different fertilization in paddy field and develop water quality model, mass balance analysis was performed during growing season of 2001-2002 in field experimental plots irrigated with groundwater. As a result of water balance analysis, most of outflow was surface drainage as about half of total outflow and about 500mm was lost by evapotranspiration. The water budget was well balanced. The runoff from paddy field was influenced by rainfall and forced drain. Especially runoff during early cultural periods more depends on the forced drain. As a result of mass balance analysis, most of nutrient was input by fertilization and lost by plant uptake. Significant amount of nitrogen were supplied by precipitation and input from upper paddy field, comprising 12%∼28% of total inflow. Nutrient loading by surface drainage was occurred showing about 15%∼29% for T-N and 6%∼13% for T-P. The response of rice yield with different fertilization was not significant in this study. Water quality model for paddy field developed using Dirac delta function and continuous source was calibrated and validated to surface water quality monitoring data. It demonstrates good agreement between observed and simulated. The nutrient concentration of surface water at paddy field was significantly influenced by fertilization. During early cultural periods when significant amount of fertilizer was applied, surface drainage from paddy field can cause serious water quality problem. Therefore, reducing surface drainage during fertilization period can reduce nutrient loading from paddy fields. Shallow irrigation, raising the weir height in diked rice fields, and minimizing forced surface drainage are suggested to reduce surface drainage outflow.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권3호
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• pp.146-153
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• 2006

We have been investigating InGaAs HEMTs as a future high-speed and low-power logic technology for beyond CMOS applications. In this work, we have experimentally studied the role of the side-recess spacing $(L_{side})$ on the logic performance of 50 nm $In_{0.7}Ga_{0.3}As$ As HEMTs. We have found that $L_{side}$ has a large influence on the electrostatic integrity (or short channel effects), gate leakage current, gate-drain capacitance, and source and drain resistance of the device. For our device design, an optimum value of $L_{side}$ of 150 nm is found. 50 nm $In_{0.7}Ga_{0.3}As$ HEMTs with this value of $L_{side}$ exhibit $I_{ON}/I_{OFF}$ ratios in excess of $10^4$, subthreshold slopes smaller than 90 mV/dec, and logic gate delays of about 1.3 ps at a $V_{CC}$ of 0.5 V. In spite of the fact that these devices are not optimized for logic, these values are comparable to state-of-the-art MOSFETs with similar gate lengths. Our work confirms that in the landscape of alternatives for beyond CMOS technologies, InAs-rich InGaAs FETs hold considerable promise.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권1호
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• pp.22-29
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• 2006

We demonstrate highly manufacturable Multi-channel Field Effect Transistor (McFET) on bulk Si wafer. McFET shows excellent transistor characteristics, such as $5{\sim}6 times higher drive current than planar MOSFET, ideal subthreshold swing, low drain induced barrier lowering (DIBL) without pocket implantation and negligible body bias dependency, maintaining the same source/drain resistance as that of a planar transistor due to the unique feature of McFET. And suitable threshold voltage ($V_T$) for SRAM operation and high static noise margin (SNM) are achieved by using TiN metal gate electrode.

• 센서학회지
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• 제23권2호
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• pp.114-121
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• 2014

We report a polysilicon active area membrane field effect transistor (PSAFET) pressure sensor for low stress deflection of membrane. The PSAFET was produced in conventional FET semiconductor fabrication and backside wet etching. The PSAFET located at the front side measured pressure change using 300 nm thin-nitride membrane when a membrane was slightly strained by the small deflection of membrane shape from backside with any physical force. The PSAFET showed high sensitivity around threshold voltage, because threshold voltage variation was composed of fractional function form in sensitivity equation of current variation. When gate voltage was biased close to threshold voltage, a fractional function form had infinite value at $V_{tn}$, which increased the current variation of sensitivity. Threshold voltage effect was dominant right after the PSAFET was turned on. Narrow transistor channel established by small current flow was choked because electron could barely cross drain-source electrodes. When gate voltage was far from threshold voltage, threshold voltage effect converged to zero in fractional form of threshold voltage variations and drain current change was mostly determined by mobility changes. As the PSAFET fabrication was compatible with a polysilicon FET in CMOS fabrication, it could be adapted in low pressure sensor and bio molecular sensor.

• 대한전자공학회논문지
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• 제27권11호
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• pp.49-54
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• 1990

본 논문에서는 LDD(lightly doped drain)구조를 갖는 짧은 채널 MOSFET에서의 기생저항의 게이트 전압 의존도에 대한 모형을 제시하였다. 게이트 전극 밑에 위치한 LDD 영역에서는 게이트 전압에 의해 준 이차원적인 축적층(quasi two-dimensional accumulation layer)이 형성된다. 소오스 측 LDD 기생저항을 축적층의 저항과 벌크 LDD 저항의 병렬 연결로 취급하였으며 별크 LDD 저항은 채널의 반전층 끝으로부터 ${n^+}$영역의 경계까지 퍼짐 저항으로 근사하였다. 그리고 접합에서의 도우핑 농도 구배가 LDD 저항에 미치는 영향이 토의하였다. 본 모형의 결과로 선형 영역에서는 LDD 저항이 게이트 전압의 증가에 따라 감소하고, 포화영역에서는 채널과 LDD에서 속도포화를 고려한 결과, 게이트 전압에 대해 준 일차적으로 증가하는 것으나 나타나 발표된 실험결과들과 일치하였다.