• Title/Summary/Keyword: source/drain

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Electrical properties of SOI n-MOSFET's under nonisothermal lattice temperature (격자온도 불균일 조건에서 SOI n-MOSFET의 전기적 특성)

  • 김진양;박영준;민홍식
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.3
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    • pp.89-95
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    • 1996
  • In this ppaer, temeprature dependent transport and heat transport models have been incorperated to the two dimensional device simulator SNU-2D provides a solid bse for nonisothermal device simulation. As an example to study the nonisothermal problem. we consider SOI MOSFET's I-V characteristics have been simulated and compared with the measurements. It is shown that negative slopes in the Ids-Vds characteristics are casused by the temperature dependence of the saturation velocity and the degradation of the temperature dependence mobility. Also it is shown that the kink effect occurs when impact ionization near the drain produces a buildup of holes in this isolated device island, and the hysteresis is caused by the creation of holes in the channel and their flow to the source.

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Analysis of MODFET Transport using Monte-Carlo Algorithm ` Gate Length Dependent Characteristics (몬테칼로 알고리즘을 이용한 MODFET소자의 전달특성분석;채널길이에 따른 특성분석)

  • Hak Kee Jung
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.30A no.4
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    • pp.40-50
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    • 1993
  • In this paper, MODFET devices with various gate length are simulated using the Monte-Carlo method. The number of superparticle is 5000 and the Poisson equation is solved to obtain field distribution. The structure of MODFET is n-AlGaAs/i-AlGaAs/iGaAs and doping concentration of n-AlGaAs layer is 1${\times}10^{17}/cm^{3}$ and the thickness is 500.angs., and the thickness of i-AlGaAs is 50$\AA$. The devices with gate length 0.2$\mu$m, 0.5$\mu$m, 1.0$\mu$m respctively are simulated and the current-voltage curves and transport characteristics of that devices are obtained. Occupancy of each subband and electron energy distribution and conduction energy band in channel have been analyzed to obtain transport characteristics, and particles transposed from source to drain have been analyzed to current-voltage curves. Current level is highest for the device of Lg=0.2$\mu$m and transconductance of this device is 310mS/mm.

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Analysis of Electrical Characteristics for Double Gate MOSFET (Double Gate MOSFET의 전기적 특성 분석)

  • 김근호;김재홍;고석웅;정학기
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2002.05a
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    • pp.261-263
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    • 2002
  • CMOS devices have scaled down to sub-50nm gate to achieve high performance and high integration density. Key challenges with the device scaling are non-scalable threshold voltage( $V^{th}$ ), high electric field, parasitic source/drain resistance, and $V^{th}$ variation by random dopant distribution. To solve scale-down problem of conventional structure, a new structure was proposed. In this paper, we have investigated double-gate MOSFET structure, which has the main-gate and the side-gates, to solve these problem.

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Schottky barrier Thin-Film-Transistors crystallized by Excimer laser annealing and solid phase crystallization method (ELA 결정화와 SPC 결정화를 이용한 쇼트키 장벽 다결정 실리콘 박막 트랜지스터)

  • Shin, Jin-Wook;Choi, Chel-Jong;Cho, Won-Ju
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.06a
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    • pp.129-130
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    • 2008
  • Polycrystalline silicon (poly-Si) Schottky barrier thin film transistors (SB-TFT) are fabricated by erbium silicided source/drain for n-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method. The fabricated poly-Si SB-TFTs have a large on/off current ratio with a low leakage current. Moreover, the electrical characteristics of poly-Si SB TFTs are significantly improved by the additional forming gas annealing in 2 % $H_2/N_2$, because the interface trap states at the poly-Si grain boundaries and at the gate oxide/poly-Si channel decreased.

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Electrical Properties of CuPc Field-effect Transistor with Different Electrodes (전극 변화에 따른 CuPc Field-effect Transistor의 전기적 특성)

  • Lee, Ho-Shik;Park, Yong-Pil;Cheon, Min-Woo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.06a
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    • pp.506-507
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    • 2008
  • Organic field-effect transistors (OFETs) are of interest for use in widely area electronic applications. We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with different metal electrode. The CuPc FET made a top-contact type and the substrate temperature was room temperature. The source and drain electrodes were used an Au and Al materials. The CuPc thickness was 40nm, and the channel length was $50{\mu}m$, channel device was width was 3mm. We observed a typical current-voltage (I-V) characteristics in CuPc FET with different electrode materials.

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Electrical Properties of CuPc Field-effect Transistor with Different Electrodes (전극에 따른 CuPc Field-effect Transistor의 전기적 특성)

  • Lee, Ho-Shik;Park, Yong-Pil;Cheon, Min-Woo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.04b
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    • pp.12-13
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    • 2008
  • Organic field-effect transistors (OFETs) are of interest for use in widely area electronic applications. We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with different metal electrode. The CuPc FET device was made a top-contact type and the substrate temperature was room temperature. The source and drain electrodes were used an Au and Al materials. The CuPc thickness was 40nm, and the channel length was $50{\mu}m$, channel width was 3mm. We observed a typical current-voltage (I-V) characteristics in CuPc FET with different electrode materials.

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Investigation on the Doping Effects on L-shaped Tunneling Field Effect transistors(L-shaped TFETs) (도핑효과에 의한 L-shaped 터널링 전계효과 트랜지스터의 영향에 대한 연구)

  • Shim, Un-Seong;Ahn, Tae-Jun;Yu, Yun Seop
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2016.05a
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    • pp.450-452
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    • 2016
  • The effect of channel doping on L-shaped Tunneling Field-Effect Transistors (TFETs) have been investigated by 2D TCAD simulation. When the source doping is over $10^{20}cm^{-3}$, the subthreshold swing (SS) is abruptly decreased, and when drain doping concentration is below $10^{18}cm^{-3}$, the leakage current in the negative voltage is reduced.

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Enhanced Performance of Solution-Processed n-channel Organic Thin Film Transistor with Electron-Donating Injection Layer

  • Kim, Sung-Hoon;Lee, Sun-Hee;Han, Seung-Hoon;Choi, Min-Hee;Jeong, Yong-Bin;Jang, Jin
    • 한국정보디스플레이학회:학술대회논문집
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    • 2009.10a
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    • pp.64-66
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    • 2009
  • We obtained high performance of n-type organic thin film transistors (OTFTs) using a solution process. N, N' bis-(octyl-)-dicyanoperylene-3,4:9,10-bis(dicarboximide) (PDI-$8CN_2$) in ambient air. Low work function interlayer on source/drain is needed to enhance the electron injection to low LUMO level of n-type organic semiconductor. By using self-assembled monolayer (SAM) the field-effect mobility of 0.33 $cm^2$/Vs was achieved.

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Metal Oxide/Metal Bi-layer for Low-Cost Source/Drain Contact of Pentacene OTFT

  • Moon, Han-Ul;Yoo, Seung-Hyup
    • 한국정보디스플레이학회:학술대회논문집
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    • 2009.10a
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    • pp.571-574
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    • 2009
  • Metal oxide/metal bilayer structures are explored as contacts with a low injection barrier in organic thin-film transistors (OTFTs) in an effort to realize their true potential for low-cost electronics. OTFTs with a bilayer electrode of $WO_3$ (10nm) and Al shows a saturation mobility as large as 0.97 $cm^2$/Vsec which are comparable to those of Au-based control samples (~0.90 $cm^2$/Vsec). Scaling of contact resistance with respect to the thickness of $WO_3$ layer is also discussed.

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