• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.1115-1118
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• 2006

Using a thermally-crosslinkable organosiloxane-based organic-inorganic hybrid material, solution processable gate dielectric layer for organic thin-film transistors (OTFTs) have been fabricated. The hybrid dielectrics are synthesized by the sol-gel process, followed by the heat-treatment at $190{\bullet}\;.{\bullet}$ To investigate the electrical property of hybrid dielectric, leakage current behavior and capacitance were measured. To fabricate coplanar-type OTFTs, Au/Cr electrode was deposited onto the heavily doped silicon substrate with the organic-inorganic hybrid dielectric layer and then ${\alpha},{\omega}-dihexylquaterthiophene$ was drop-cast between source and drain electrical performance of the fabricated transistor.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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• pp.1413-1415
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• 2005

The OTFT performance depends strongly on the interfacial properties between an organic semiconductor and ${\alpha}$ metal electrode. The contact resistance is critical to the current flow in the device. The contact resistance arises mainly from the Schottky barrier formation due to the work function difference between the semiconductor and electrodes. We doped pentacene/source-drain interfaces with $F_4TCNQ$ (2,3,5,6-Tetrafluoro-7,7,8,8-tetracyanoquinodimethane), resulting in p-doped region at the SD contacts, in order to solve this problem. We found that the mobility increased and the threshold voltage decreased.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.149-152
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• 2003

Soruce/drain (or, LDD) formation technology is critical to device reliability especially in the case of short channel LTPS-TFT devices. Ion shower doping with a main ion source of $P_2H_x$ was conducted on ELA Poly-Si. We report the effects of annealing methods on dopant activation and damage recovery in ion-shower doped poly-Si.

• Journal of Information Display
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• 제13권1호
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• pp.51-54
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• 2012

In this study, the bias-temperature stress and current-temperature stress induced by the electrical stabilities of half-Corbino hydrogenated-amorphous-silicon (a-Si:H) thin-film transistors (TFTs) with different gate electrode geometries fabricated on the same substrate were examined. The influence of the gate pattern on the threshold voltage shift of the half-Corbino a-Si:H TFTs is discussed in this paper. The results indicate that the half-Corbino a-Si:H TFT with a patterned gate electrode has enhanced power efficiency and improved aperture ratio when compared with the half-Corbino a-Si:H TFT with an unpatterned gate electrode and the same source/drain electrode geometry.

• Journal of Information Display
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• 제12권4호
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• pp.213-217
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• 2011

Printing technologies were applied to fabricate a flexible organic thin-film transistor (OTFT) backplane for electrophoretic displays (EPDs). Various printing processes were adopted to maximize the figures of each layer of OTFT: screen printing combined with reverse offset printing for the gate electrodes and scan bus lines with Ag ink, inkjet for the source/drain electrodes with glycerol-doped Poly (3,4-ethylenedioxythiophene): Poly (styrenesulfonate) (PEDOT:PSS), inkjet for the semiconductor layer with Triisopropylsilylethynyl (TIPS)-pentacene, and screen printing for the pixel electrodes with Ag paste. A mobility of $0.44cm^2/V$ s was obtained, with an average standard deviation of 20%, from the 36 OTFTs taken from different backplane locations, which indicates high uniformity. An EPD laminated on an OTFT backplane with $190{\times}152$ pixels on an 8-in panel was successfully operated by displaying some patterns.

• 한국전기전자재료학회논문지
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• 제14권2호
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• pp.123-129
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• 2001

The optimal high temperature processing conditions for the formation of Ohmic contact of Ti/Al/Pt/Au multiple layers were established for the fabrication of n$^{+}$-GaN/AlGaN/GaN HFET device. Contact resistivity as low as 3.4x10$^{-6}$ ohm-$\textrm{cm}^2$ was achieved by the annealing of the sample at 100$0^{\circ}C$ for 10 sec. using the RTA (Rapid Thermal Annealing) system. The fabricated HFET (Heterostructure Field Effect Transistor) with a structure of n'-GaN/undoped AlGaN/undoped GaN exhibited a low knee voltage of 3.5 V and a maximum source-drain current density of 180 mA/mm at Vg=0V.V.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 C
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• pp.1515-1517
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• 2001

In this work the electrical characteristics of organic TFTs with the semiconductor-insulator interfaces have been interested. Pentacene is used as an active semiconducting layer. The semiconductor layer of pentacene was thermally evaporated in vacuum at a pressure of about $2{\times}10^{-6}$ Torr and at a deposition rate of 0.3$\AA$/sec. Aluminium and gold were used for gate and source/drain electrodes. before pentacene is deposited on the insulator, the gate dielectric surfaces of two samples were rubbed with lateral and perpendicular to direction of the channel length respectively.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.355-355
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• 2010

We studied the dependence of the performance of schottky barrier metal-oxide-field effect transistors(SB MOSFETs) on the work function of source/drain metals. A strong impact of the various work functions and the light wavelengths on the transistor characteristics is found and explained using experimental data. We used an insulator of a high thickness (100nm) and back gate issues in SOI substrate, subthreshold swing was measured to 300~400[mV/dec] comparing with a ideal subthreshold swing of 60[mV/dec]. Excellent characteristics of Al/Si was demonstrated higher on/off current ratios of ${\sim}10^7$ than others. In addition, extensive photoresponse analysis has been performed using halogen and deuterium light sources(200<$\lambda$<2000nm).

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.356-356
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• 2010

In this paper, Poly silicon thin-film transistors (poly-Si TFTs) with employed the SPC (Solid phase crystallization) and ELA (Excimer laser annealing) methods on glass panel substrate are fabricated to investigate the electrical poperies. Poly-Si TFTs have recess-channel structure with formated source/drain regions by LPCVD n+ poly Si in low $650^{\circ}C$ temperature. the ELA-TFT show higher on/off current ratio and subthreshold swing than a-Si and SPC TFT that therefore, these results showed that the ELA-TFT might be beneficial for practical embedded TFT memory device application.

• 한국전기전자재료학회논문지
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• 제21권10호
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• pp.930-933
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• 2008

Organic field-effect transistors (OFETs) are of interest for use in widely area electronic applications. We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with different metal electrode. The CuPc FET device was made a top-contact type and the substrate temperature was room temperature. The source and drain electrodes were used an Au and Al materials. The CuPc thickness was 40 nm, and the channel length was $50{\mu}m$, channel width was 3 mm. We observed a typical current-voltage (I-V) characteristics in CuPc FET with different electrode materials.