• 한국정보통신학회논문지
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• 제21권1호
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• pp.82-89
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• 2017

본 연구에서는 소스 및 드레인 전극 재료에 따른 소자 열화를 분석하기 위해 Ni, Al, 및 ITO를 소스 및 드레인 전극 재료로 사용하여 InGaZnO 박막 트랜지스터를 제작하였다. 전극 재료에 따른 소자의 전기적 특성을 분석한 결과 Ni 소자가 이동도, 문턱전압 이하 스윙, 구동전류 대 누설전류 비율이 가장 우수하였다. 소스 및 드레인 전극 재료에 따른 소자 열화 측정결과 Al 소자의 열화가 가장 심한 것을 알 수 있었다. InGaZnO 박막 트랜지스터의 소자 열화 메카니즘을 분석하기 위하여 채널 폭과 스트레스 드레인 전압을 다르게 하여 문턱전압 변화를 측정하였다. 그 결과 채널 폭이 넓을수록 또 스트레스 드레인 전압이 높을수록 소자 열화가 많이 되었다. 측정결과로부터 InGaZnO 박막 트랜지스터의 소자 열화는 큰 채널 전계와 주울 열의 결합 작용으로 발생함을 알 수 있었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 C
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• pp.1085-1087
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• 1995

A large leakage current may be one of the critical issues for poly-silicon thin film transistors(poly-Si TFTs) for LCD applications. In order to reduce the leakage current of poly-Si TFTs, several offset gated structures have been reported. However, those devices, where the offset length in the source region is not same as that in the drain region, exhibit the asymmetric electrical performances such as the threshold voltage shift and the variation of the subthreshold slope. The different offset length is caused by the additional mask step for the conventional offset structures. Also the self-aligned implantation may not be applicable due to the mis-alignment problem. In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photo resistor reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate from both sides of the main gate. The poly-Si channel layer below the offset oxide is protected from the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of our new device is the offset lesion due to the offset oxide. Our experimental results show that the offset region, due to the photo resistor reflow process, has been successfully obtained in order to fabricate the offset gated poly-Si TFTs. The advantages of the proposed device are that the offset length in the source region is the same as that in the drain region because of the self-aligned implantation and the proposed device does not require any additional mask process step.

• 한국정보통신학회논문지
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• 제13권6호
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• pp.1123-1127
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• 2009

본 연구는 비정질실리콘 박막트랜지스터를 비휘발성 메모리소자로 제작함으로써 스위칭 소자로 사용되는 박막 트랜지스터(TFT)의 응용범위를 확대시키고, 비정질 실리콘 사용에 따라 대면적화에 적합하고 아울러 값싼 기판을 사용할 수 있게 한 비정질 실리콘 비휘발성 메모리소자에 관한 것이다. 이와 같은 본 연구는 유리기판과 그 유리기판위에 증착시켜 패터닝한 게이트, 그 게이트를 덮어씌운 제1 절연층, 그 제1 절연층위에 증착시켜 패터닝한 플로우팅 게이트와 그 플로우팅 게이트를 덮어씌운 제2 절연층, 그 제2 절연층위에 비정질실리콘을 증착시킨 액티브층과 그 액티브층위에 n+ 비정질실리콘을 증착시켜 패터닝한 소오스/드레인층 그리고 소오스/드레인층 위에 증착시킨 소오스/드레인층 전극으로 비정질실리콘 박막트랜지스터 비휘발성 메모리소자를 구성한다.

• 한국전기전자재료학회논문지
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• 제21권9호
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• pp.835-843
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• 2008

We have fabricated the source-drain electrodes for OTFTs by screen printing method and manufactured Ag pastes as conductive paste. To obtain excellent conductivity and screen-printability of Ag pastes, the dispersion characteristics of Ag pastes prepared from two types of acryl resins with different molecular structures and Ag powder treated with caprylic acid, triethanol amine and dodecane thiol as surfactant respectively were investigated. The Ag pastes containing Ag powder treated with dodecane thiol having thiol as anchor group or AA4123 with carboxyl group(COOH) of hydrophilic group as binder resin exhibited excellent dispersity. But, Ag pastes(CA-41, TA-41, DT-41) prepared from AA4123 fabricated the insulating layer since the strong interaction between surface of Ag powder and carboxyl group(COOH) of AA4123 interfered with the formation of conduction path among Ag powders. The viscosity behavior of Ag pastes exhibited shear-thinning flow in the high shear rate range and the pastes with bad dispersion characteristic demonstrated higher shear-thinning index than those with good dispersity due to the weak flocculated network structure. The output curve of OTFT device with a channel length of 107 ${\mu}m$ using screen-printed S-D electrodes from DT-30 showed good saturation behavior and no significant contact resistance. And this device exhibited a saturation mobility of $4.0{\times}10^{-3}$ $cm^2/Vs$, on/off current ratio of about $10^5$ and a threshold voltage of about 0.7 V.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 추계학술대회 논문집
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• pp.506-508
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• 2005

In general, organic TFTs are comprised of four components: gate electrode, gate dielectric, organic active semiconductor layer, and source and drain contacts. The TFT current, in turn, is typically determined by channel length and width, carrier field effect mobility, gate dielectric thickness and permittivity, contact resistance, and biasing conditions. More recently, a number of techniques and processes have been introduced to the fabrication of OTFT circuits and displays that aim specifically at reduced fabrication cost. These include microcontact printing for the patterning of metals and dielectrics, the use of photochemically patterned insulating and conducting films, and inkjet printing for the selective deposition of contacts and interconnect pattern. In the fabrication of organic TFTs, microcontact printing has been used to pattern gate electrodes, gate dielectrics, and source and drain contacts with sufficient yield to allow the fabrication of transistors. We were fabricated a pentacene OTFTs on flexible PEN film. Au/Cr was used for the gate electrode, parylene-c was deposited as the gate dielectric, and Au/Cr was chosen for the source and drain contacts; were all deposited by ion-beam sputtering and patterned by microcontact printing and lift-off process. Prior to the deposition of the organic active layer, the gate dielectric surface was treated with octadecyltrichlorosilane(OTS) from the vapor phase. To complete the device, pentacene was deposited by thermal evaporation and patterned using a parylene-c layer. The device was shown that the carrier field effect mobility, the threshold voltage, the subthreshold slope, and the on/off current ratio were improved.

• 한국전기전자재료학회논문지
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• 제16권1호
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• pp.5-10
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• 2003

In this study, a new programming method to minimize the generation of Si-SiO$_2$interface traps of SONOS nonvolatile memory device as a function of number of porgram/erase cycles was proposed. In the proposed programming method, power supply voltage is applied to the gate. forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim(MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and dram are left open. Also, the asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics or SONOS devices because electrical stress applied to the Si-SiO$_2$interface is reduced due to short program time.

• 대한전기학회논문지:시스템및제어부문D
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• 제52권5호
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• pp.290-294
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• 2003

Using a backpropagation neural network (BPNN), a high power semiconductor device was empirically modeled. The device modeled is a n-LDMOSFET and its electrical characteristics were measured with a HP4156A and a Tektronix curve tracer 370A. The drain-source current $(I_{DS})$ was measured over the drain-source voltage $(V_{DS})$ ranging between 1 V to 200 V at each gate-source voltage $(V_{GS}).$ For each $V_{GS},$ the BPNN was trained with 100 training data, and the trained model was tested with another 100 test data not pertaining to the training data. The prediction accuracy of each $V_{GS}$ model was optimized as a function of training factors, including training tolerance, number of hidden neurons, initial weight distribution, and two gradients of activation functions. Predictions from optimized models were highly consistent with actual measurements.

• 폴리머
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• 제33권5호
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• pp.397-406
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• 2009

유기 박막 트랜지스터 (OTFTs)의 소스-드레인 전극을 스크린 인쇄를 통해 제작하였고, 전극용 페이스트로써 전도성 카본블랙 페이스트를 사용하였다. 전도성 카본블랙 페이스트를 제조하기 위해 서로 다른 분자량 및 고분자 사슬 구조를 갖는 2종류의 분산제(DB-2150, DB-9077)를 사용하여 분산제 함량(SOF; solid on powder, 10-40%)에 따른 카본블랙 밀베이스의 분산 특성을 검토한 결과, 분산제 함량이 증가함에 따라 분산 특성이 더 우수해 짐을 알 수 있었다. 전도성 카본블랙 페이스트를 제조하여 레올로지 측정을 통해 카본블랙의 분산상태 및 응집구조에 대해 검토한 결과, 분산제로 DB-2150을 사용한 페이스트들은 분산제 함량이 증가함에 따라 페이스트의 분산 특성이 향상되어 저장 탄성률(G')이 감소하였지만, DB-9077을 사용한 페이스트들은 카본블랙 사이의 상호작용에 의해 망목구조가 존재하였고, 분산제 함량이 증가함에 따라 카본블랙과 분산제간 또는 분산제간의 상호작용에 의해 페이스트의 저장 탄성률(G')은 더욱 증가하였다. 이러한 응집구조는 페이스트의 내부 저항력 (tacky)을 발생시켜 DB-9077을 사용한 페이스트들은 분산제 함량이 증가함에 따라 스크린 인쇄 적성이 좋지 못하였다. 하지만, 스크린 인쇄된 OTFTs용 소스-드레인 전극의 전기적 특성은 카본블랙 사이에 형성된 망목구조에 의해 카본블랙의 도전 경로(conduction Path)가 형성됨에 따라 DB-2150을 사용한 페이스트들의 OTFTs에 비해 더 우수하였다. 그러나, 2종류의 분산제를 사용한 페이스트 모두, 분산제의 함량이 증가함에 따라 카본블랙 표면을 감싸는 분산제 함량 또한 증가하게 되어 이로 인해 카본블랙간의 도전 경로 형성은 어렵게 되고 전극의 특성은 점점 열화되었다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권1호
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• pp.24-29
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• 2000

We propose a simple method to control the crystallization depth of amorphous silicon (a-Si) deposited by PECVD or LPCVD during the excimer laser annealing (ELA). Employing the new method, we have formed poly-Si/a-Si double film and fabricated a new poly-Si TFT with vertical a-Si offsets between the poly-Si channel and the source/drain of TFT without any additional photo-lithography process. The maximum leakage current of the new poly-Si TFT decreased about 80% due to the highly resistive vertical a-Si offsets which reduce the peak electric field in drain depletion region and suppress electron-hole pair generation. In ON state, current flows spreading down through broad a-Si cross-section in the vertical a-Si offsets and the current density in the drain depletion region where large electric field is applied is reduced. The stability of poly-Si TFT has been improved noticeably by suppressing trap state generation in drain region which is caused by high current density and large electric field. For example, ON current of the new TFT decreased only 7% at a stress condition where ON current of conventional TFT decreased 89%.

• 한국전기전자재료학회논문지
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• 제25권9호
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• pp.671-676
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• 2012

In this paper, TCAD assessment of 30-V class n-channel EDMOS (extended drain metal-oxide-semiconductor) transistors with DWFG (dual work function gate) structure are described. Gate of the DWFG EDMOS transistor is composed of both p- and n-type doped region on source and drain side. Additionally, lengths of p- and n-type doped gate region are varied while keeping physical channel length. Two-dimensional device structures are generated trough TSUPREM-4 and their electrical characteristics are investigated with MEDICI. The DWFG EDMOS transistor shows improved electrical characteristics than conventional device - i.e. higher transconductance ($g_m$), better drain output current ($I_{ON}$), reduced specific on-resistances ($R_{ON}$) and higher breakdown characteristics ($BV_{DSS}$).