• Title/Summary/Keyword: small time-delay process

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PID Controller Tuning Rules Using an Inner P Controller (내부 P제어를 이용한 PID 제어기 튜닝규칙)

  • Kim, Dong-Il;Sung, Su-Whan;Lee, Jie-Tae
    • Journal of Institute of Control, Robotics and Systems
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    • v.12 no.12
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    • pp.1173-1177
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    • 2006
  • Using an inner P controller, a tuning rule useful for processes with wide ratios of time delay over time constant is proposed. Internal model control method and pole assignment method are utilized. It can be used for processes with wide range of the ratio of time delay to time constant without incovenience to choose different tuning rules.

A delay model for CMOS inverter (CMOS 인버터의 지연 시간 모델)

  • 김동욱;최태용;정병권
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.34C no.6
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    • pp.11-21
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    • 1997
  • The delay models for CMOS invertr presented so far predicted the delay time quite accurately whens input transition-time is very small. But the problem that the accuracy is inclined to decrease becomes apparent as input transition tiem increases. In this paper, a delay model for CMOS inverter is presented, which accuractely predicts the delay time even though input transition-time increases. To inverter must be included in modeling process because the main reason of inaccuracy as input transition tiem is the leakage current through the complementary MOS. For efficient modeling, this paper first models the MOSes with simple I-V charcteristic, with which both the pMOS and the nMOS are considered easily in calculating the inverter delay times. This resulting model needs few parameters and re-models each MOS effectively and simply evaluates output voltage to predict delay time, delay values obtained from this effectively and simply evaluates output voltage to predict delay time, delay values obtained from this model have been found to be within about 5% error rate of the SPICE results. The calculation time to predict the delay time with the model from this paper has the speed of more than 70times as fast as to the SPICE.

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Speed Control for Low Speed Diesel Engine by Hybrid F-NFC (Hybrid F-NFC에 의한 저속 디젤 기관의 속도 제어)

  • Choi, G.H.;Yang, J.H.
    • Journal of Power System Engineering
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    • v.10 no.4
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    • pp.159-164
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    • 2006
  • In recent, the marine engine of a large size is being realized a lower speed, longer stroke and a small number of cylinders for the energy saving. Consequently the variation of rotational torque became larger than former days because of the longer delay-time in fuel oil injection process and an increased output per cylinder. It was necessary that algorithms have enough robustness to suppress the variation of the delay-time and the parameter perturbation. This paper shows the structure of hybrid F-NFC against the delay-time and the perturbation of engine parameter as modeling uncertainties, and the design of the robust speed controller by hybrid F-NFC for the engine. And, The Parameter values of linear equation are determined by RC-GA for F-NFS. The hybrid F-NFC is combined the F-NFC and PID controller for filling up each.

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Electrical Characteristics of BLC, MTG Adders Using $2{\mu}m$ CMOS Process ($2{\mu$}$ CMOS 공정을 이용한 BLC, MTG 가산기의 전기적 특성)

  • 이승호;신경욱;이문기
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.27 no.1
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    • pp.59-67
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    • 1990
  • In this paper, BLC adder/subtractor and MTG adder which can be used as a fundamental operation block in VLSI processors are designed, and their structural and electrical characteristics are analyzed and compared. Also, two circuits are fabricated usign 2\ulcorner CMOS process and their time delays for critical paths are measured. For 8 bit binary addition, the measured critical delays for MSB sum of the BLC adder/subtractor are 26 nsec for rising delay and 32nsec for falling. Those for MSB carry out of the MTG adder are 28nsed and 38nsec, respectively. The BLC adder/subtractor has a layout area which is 4 times larger than the MTG adder, and a fast operation speed. On the contrary, the MTG adder has a small layout area and a large time delay.

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Design of High-Speed Sense Amplifier for In-Memory Computing (인 메모리 컴퓨팅을 위한 고속 감지 증폭기 설계)

  • Na-Hyun Kim;Jeong-Beom Kim
    • The Journal of the Korea institute of electronic communication sciences
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    • v.18 no.5
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    • pp.777-784
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    • 2023
  • A sense amplifier is an essential peripheral circuit for designing a memory and is used to sense a small differential input signal and amplify it into digital signal. In this paper, a high-speed sense amplifier applicable to in-memory computing circuits is proposed. The proposed circuit reduces sense delay time through transistor Mtail that provides an additional discharge path and improves the circuit performance of the sense amplifier by applying m-GDI (: modified Gate Diffusion Input). Compared with previous structure, the sense delay time was reduced by 16.82%, the PDP(: Power Delay Product) by 17.23%, the EDP(: Energy Delay Product) by 31.1%. The proposed circuit was implemented using TSMC's 65nm CMOS process, while its feasibility was verified through SPECTRE simulation in this study.

Hardware Implementation of Time Skew Calibration Block for Time Interleaved ADC (TI ADC를 위한 시간 왜곡 교정 블록의 하드웨어 구현)

  • Khan, Sadeque Reza;Choi, Goangseog
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.13 no.3
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    • pp.35-42
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    • 2017
  • This paper presents hardware implementation of background timing-skew calibration technique for time-interleaved analog-to-digital converters (TI ADCs). The timing skew between any two adjacent analog-digital (A/D) channels is detected by using pure digital Finite Impulse Response (FIR) delay filter. This paper includes hardware architecture of the system, main units and small sub-blocks along with control logic circuits. Moreover, timing diagrams of logic simulations using ModelSim are provided and discussed for further understanding about simulations. Simulation process in MATLAB and Verilog is also included and provided with basic settings need to be done. For hardware implementation it not practical to work with all samples. Hence, the simulation is conducted on 512 TI ADC output samples which are stored in the buffer simultaneously and the correction arithmetic is done on those samples according to the time skew algorithm. Through the simulated results, we verified the implemented hardware is working well.

Development of Operation Network System and Processor in the Loop Simulation for Swarm Flight of Small UAVs (소형 무인기들의 군집비행을 위한 운영 네트워크 시스템과 PILS 개발)

  • Kim, Sung-Hwan;Cho, Sang-Ook;Cho, Seong-Beom;Park, Choon-Bae
    • Journal of Institute of Control, Robotics and Systems
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    • v.18 no.5
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    • pp.433-438
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    • 2012
  • In this paper, a operation network system equipped with onboard wireless communication systems and ground-based mission control systems is proposed for swarm flight of small UAVs. This operating system can be divided into two networks, UAV communication network and ground control system. The UAV communication network is intend to exchange the informations of navigation, mission and flight status with minimum time delay. The ground control system consisted of mission control systems and UDP network. Proposed operation network system can make a swarm flight of various UAVs, execute complex missions decentralizing mission to several UAVs and cooperte several missions. Finally, PILS environments are developed based on the total operating system.

Implementation of micro-magnetic detection system based on wireless sensor networks (무선센서네트워크 기반의 미소자기감지 시스템 개발)

  • Lee, Young-Dong;Park, Jong-Hun;Kang, Hag-Seong
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2014.05a
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    • pp.402-403
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    • 2014
  • Micro-magnetic detection system is used to detect small particles in an automatic transmission valve body, which signal noise and time-delay may occurs in process of signal transmitting and filtering. In this paper, we present the design and implement of a micro-magnetic detection system based on wireless sensor networks. Micro-magnetic detection system consists of five modules which are magnetic sensor detector, signal processing unit, wireless sensor networks, system control unit and system monitoring unit. The experimental results show that signal noise and time-delay decreased.

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Design of Robust Servo Controller for Large Size Low Speed Diesel Engines (대형 저속 디젤기관의 속도제어를 위한 로바스트 서보 제어기 설계)

  • Jeong, Byeong-Geon;Yang, Ju-Ho;Byeon, Jeong-Hwan
    • Journal of the Korean Society of Fisheries and Ocean Technology
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    • v.33 no.1
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    • pp.46-58
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    • 1997
  • The energy saving is one of the most important factors for profit in marine transportation. In order to reduce the fuel oil consumtion the ship's propulsion efficiency must be increased as possible. The propulsion efficiency depends upon a combination of an engine and a propeller. The propeller has better efficiency as lower rotational speed. This situation led the engine manufacturers to design the engine that has low speed, long stroke and a small number of cylinders. Consequently, the variation of rotational torque became larger than before because of the longer delay-time in fuel oil injection process and an increased output per cylinder. As this new trends the conventional mechanical-hydrualic governors for engine speed control have been replaced by digital speed controllers which adopted the PID control or the optimal control algorithm. But these control algorithms have not enough robustness to suppress the variation of the delay-time and the parameter perturbation. In this paper we consider the delay-time and the perturbation of engine parameters as the modeling uncetainties. Next we design the robust servo controller which has zero offset in steady state engine speed, based on H sub($\infty$) control theory. The validity of the controller was investigated through the response simulation. We used a personal computer and an analog computer as the digital controller and the engine (plant) part respectively. And, we could certify that the designed controller maintains its robust servo performance even though the engine parameters may vary.

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A speed controller design for low speed marine diesel engine by the $\mu$-synthesis ($\mu$-설계법에 의한 저속 박용디젤기관의 속도제어기 설계)

  • 정병건;양주호;김창화
    • Journal of Advanced Marine Engineering and Technology
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    • v.19 no.1
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    • pp.60-70
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    • 1995
  • In the field of marine transportation the energy saving is one of the most important factors for profit. In order to reduce the fuel oil consumption the ship's propulsion efficiency must be increased as much as possible. The propulsion efficiency depends upon a combination of an engine and a propeller. The propeller has better efficiency as lower rotational speed. This situation led the engine manufacturers to design the engine that has lower speed, longer stroke and a small number of cylinders. Consequently the variation of rotational torque became larger than before because of the longer delay-time in the fuel oil injection process and an increased output per cylinder. As this new trends the conventional mechanical-hydrualic governors for engine speed control have been replaced by digital speed controllers which adopted the PID control or the optimal control algorithm. But these control algorithms have not enough robustness to suppress the variation of the delay-time and the parameter pertubation. In this paper we consider the delay-time and the perturbation of engine parameters as the modeling uncetainties. Next we design the controller which has zero offset in steady state engine speed, based on the two-degree-of-freedom control theory and $\mu$-synthesis. Thd validity of the controller is investigated through the response simulation. We use a personal computer and an analog computer as the digital controller and the engine (plant) part respectively. And, we certify that the designed controller maintains its performance even though the engine parameters may vary.

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