• Journal of Software Assessment and Valuation
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• v.15 no.1
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• pp.55-62
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• 2019

The needs for small size and low power consumption of information devices is being implemented with SOC technology that implements the program on a single chip in Internet of Thing. Copyright disputes due to piracy are increasing in semiconductor chips as well, arising from disputes in the chip implementation of the design house and chip implementation by the illegal use of the source code. However, since the final chip implementation is made in the design house, it is difficult to protect the copyright. In this paper, we deal with the analysis method for extracting similarity and the criteria for setting similarity judgment in the dispute of source code written in HDL language. Especially, the chip which is manufactured based on the same specification will be divided into the same configuration and the code type.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.6
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• pp.983-993
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• 2001

This paper proposed a novel chip type ceramic dielectric antenna by using the advanced meander line technique that the radiational metals are formed on the face of ceramic dielectric(8$\times$4$\times$1.5 mm, alumina) and both faces of substrate(1.0 mm thickness, FR-4). The performance of the antenna model has a good agreements between measurements and computed results. Resultly, it has a 10 dB return-loss bandwidth(2.4∼2.4835 GHz) and 1.7 dBi measured radiation gain for Bluetooth application. The proposed antenna model can overcome the limited radiation of the small-sized antenna.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.3
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• pp.35-46
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• 1999

A derotator VLSI which compensates for the frequency and phase errors of a received signal in digital communication systems was developed employing a CORDIC algorithm. The CORDIC circuit directly rotates the input signal according to the phase error information, thus is much simpler than the conventional derotator architecture which consists of a DDFS (Direct Digital Frequency Synthesizer) and a complex multiplier. Since a derotator needs only small phase error accumulation, a fast direction sequence generation method which exploits the linearity of the arctangent function in small angles is utilized in order to enhance the operating speed. The chip was designed and implemented using a $0.6\mu\textrm{m}$ triple metal CMOS process by the full custom layout method. The whole chip size is $6.8\textrm{mm}^2$ and the maximum operating frequency is 25 MHz.

• Proceedings of the KIEE Conference
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• 2005.11a
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• pp.48-50
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• 2005

As technology is developed, customers want to use many functions in one system. Manufacturers want to reach the customer's needs, make systems more small, thin, light-weight. To make them real, it is necessary to make components to be small and thin. But components of power stage are big, thick and heavy-weighted yet. especially power inductor is the most significant component. This paper proposed a novel chip-type power inductor I-type inductor. Inductor that proposed has 3225-size, 5.6uH and 1.3A of max saturation current. And it has $R_{DC}$ of $0.25{\Omega}$ which is smaller than $0.45{\Omega}$ of chip-type inductor and $0.9{\Omega}$ of coil-type inductor.

• Nuclear Engineering and Technology
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• v.56 no.8
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• pp.3076-3083
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• 2024

In this work, single photon avalanche diodes (SPADs) were fabricated using the standard 180 nm complementary metal-oxide semiconductor process. Their small size of 15-16 µ m and low operating voltage made it possible to easily integrate them with readout circuits for compact on-chip sensors, particularly those used in the radiation sensor network of a nuclear plant. Four architectures were proposed for the SPADs, with a shallow trench isolation (STI) guard ring and different depletion regions designed to demonstrate the main performance parameters in each experimental configuration. The wide absorption region structure with PSD and a deep N-well could achieve a uniform electric field, resulting in a stable dark count rate (DCR). Additionally, the STI guard ring was implanted to mitigate the premature edge breakdown. A breakdown voltage was achieved for a low operating voltage of 10.75 V. The DCR results showed 286.3 Hz per ㎛² at an excess voltage of 0.04 V. A photon detection probability of 21.48% was obtained at 405 nm.

• Proceedings of the Korea Society for Simulation Conference
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• 2002.11a
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• pp.115-121
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• 2002

The growth of semiconductor industry attracted to researchers like design, facility technique and making small size chip areas. But nowadays, cause of technology extension and oversupply and price down, yield improvement is the most important point on growth. This paper describes the computer mode]ing technique as the solutions to analyze the problem, to formalize the semiconductor manufacturing process and to build advanced manufacturing environments. The computer models are built referring an existing 8' wafer production line in Korea.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.1011-1012
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• 2006

In this paper, implementation process of standard platform for T-DMB Receiver in low-cost and small-size are following: First, implement SoC for 32 bit RISC CPU and 16 bit DSP, Hardware H.264 CODEC, Post Processor or Video Display, Audio Processor, I/O Device. Second, implement Real Time OS for flexible application. Third, propose simple architecture for interface with peripheral devices using one-chip processor.

• The Journal of the Acoustical Society of Korea
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• v.16 no.3
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• pp.86-93
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• 1997

A Design & Simulation Tools of Surface Acoustic Wave(SAW) Filters for Mobile Communication Systems, which is based on Optimization of Impulse Samples with Object Function of Amplitude, Ripple and Group Delay Characteristics, is developed and is also evaluated by designning and simulating the SAW IF Filter for PCS. In Optimization Process, fast calculation algorithm of Object Function is proposed. With this Design Tools, Transversal SAW IF Filters can be easily designed under limited conditions of small chip size and package size. It may be also applicable to wide Band Pass Filters in future Communication Systems such as FPLMTS.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.318-330
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• 2013

This paper presents a high-linearity low-noise small-size programmable gain amplifier (PGA) based on a new low-noise low-distortion differential amplifier and a proposed reconfiguration technique. The proposed differential amplifier combines an inverter-based differential pair with an adaptive biasing circuit to reduce noise and distortion. The reconfiguration technique saves the chip size by half by utilizing the same differential pair for the input transconductance and load-stage, interchangeably. Fabricated in $0.18-{\mu}m$ CMOS, the proposed PGA shows a dB-linear control range of 21dB in 16 steps from -11 dB to 10 dB with a gain error of less than ${\pm}0.33$ dB, an IIP3 of 7.4~14.5 dBm, a P1dB of -7~1.2 dBm, a noise figure of 13dB, and a 3-dB bandwidth of 270MHz at the maximum gain, respectively. The PGA occupies a chip area of $0.04mm^2$ and consumes only 1.3 mA from the 1.8 V supply.

• Journal of Sensor Science and Technology
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• v.14 no.4
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• pp.237-243
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• 2005

Strain gauge type load cell is used widely as weight sensor. However, it has problems such as noise, power consumption, high cost and big size. Semiconductor type piezoresistive pressure sensor is practically used in recent for low hysteresis, good linearity, small size, light weight and strong on vibration. In this paper, we have fabricated the piezoresistive pressure sensor and packaged the miniature weight sensor. We packaged the miniature weight sensor by flip-chip bonding between die and PCB for durability, because the weight sensor is directly contacted on a physical solid distinct from air and oil pressure. We measured the characteristics of the weight sensor, which had the output of $10{\sim}80$ mV on the weight range of $0{\sim}2$ kg. In the result, we could fabricate the weight sensor with an accuracy of 3 %FSO linearity.