• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.8
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• pp.740-743
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• 2003

A multi-layer ceramic (MLC) chip type band-pass filter (BPF) is presented. The MLC chip BPF has the benefits of low cost and small size. The BPF consists of coulped stripline resonators and coupling capacitors. The BPF is designed to have an attenuation pole at below the passband for a receiver band of IMT-2000 handset. The computer-aided design technology is applied for analysis of the BPF frequency characteristics. The passband and attenuation pole depend on the coupling between resonators and coupling capacitance. The frequency characterics of the passband and attenuation pole are analyzed with the variation of the coupling between resonators and coupling capacitance. An equivanlent circuit and structure of MLC chip BPF are proposed. The frequency characteristics of the BPF is well acceptable for IMT-2000 application.

• Journal of Platform Technology
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• v.8 no.1
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• pp.24-32
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• 2020

This paper designed and manufactured a chip mounter based on 3D printer technology that can be used for educational research or sample production to disseminate chip mounter, a core technology of SMT line. A stepper motor with open loop control is used for low cost drive design. The shortcomings of the motor's vibration and disassembly caused by the use of the step motor were compensated by the Micro-Step control method. In the chip mounter experiment, the gerber file was generated on the small chip mounter, printed at the actual size, and the solder cream was printed on the HASL-treated PCB in the same manner as the sample board fabrication. As a result of the experiment, unlike the 2012 micro components, parts such as SOIC and TQFP that require correction are twice as long as the component mounting time, but it can be confirmed that they are mounted relatively accurately. In addition, as a result of repeatedly measuring the error of the initial position 10 times, it was confirmed that a relatively small error of about 0.110mm occurs.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.2
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• pp.98-103
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• 2013

The alumina substrates that Ni electrode was printed on and the multi-layered PTCR thermistors of which composition is $(Ba_{0.998}Ce_{0.002})TiO_3+0.001MnCO_3+0.05BN$ were fabricated by a thick film process, and the effect of re-oxidation temperature on their resistivities and resistance jumps were investigated, respectively. Ni electroded alumina substrate and the multi-layered PTC thermistor were sintered at $1150^{\circ}C$ for 2 h under $PO_2=10^{-6}$ Pa and then re-oxidized at $600{\sim}850^{\circ}C$ for 20 min. With increasing the re-oxidation temperature, the room temperature resistivity increased and the resistance jump ($LogR_{290}/R_{25}$) decreased, which seems to be related to the oxidation of Ni electrode. The small sized chip PTC thermistor such as 2012 and 3216 exhibits a nonlinear and rectifying behavior in I-V curve but the large sized chip PTC thermistor such as 4532 and 6532 shows a linear and ohmic behavior. Also, the small sized chip PTC thermistor such as 2012 and 3216 is more dependent on the re-oxidation temperature and easy to be oxidized in comparison with the large sized chip PTC thermistor such as 4532 and 6532. So, the re-oxidation conditions of chip PTC thermistor may be determined by considering the chip size.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.5
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• pp.283-288
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• 2000

In this work, small-size, high-performance simple solenoid-type RF chip inductors utilizing an Al2O3 core material were investigated. Copper (Cu) wire with $40\mum$ diameter was used as the coils and the size of the chip inductor fabricated in this work was $2.1mm\times1.5mm\times1.0mm$. The external current source was applied after bonding Cu coil leads to gold pads electro-plated on each end of backsides of a core material. High frequency characteristics of the inductance (L), quality factor (Q), and impedance (Z) of developed inductors were measured using an RF Impedance/Material Analyzer (HP4291B with HP16193A test fixture). This HP4291B was also used to obtain the equivalent circuit and its circuit parameters of the chip inductors. This HP4291B was also used to obtain the equivalent circuit and its circuit parameters of the chip inductors. The developed inductors have the self-resonant frequency (SRF) of 1.1 to 3.1 GHz and exhibit L of 22 to 150 nH. The L of the inductors decreases with increasing the SRF. The Z of the inductors has the maximum value at the SRF and the inductors have the quality factor of 70 to 97 in the frequency range of 500 MHz to 1.5 GHz.

• 한국HCI학회:학술대회논문집
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• 2008.02a
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• pp.337-341
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• 2008

This paper presents a vibrotactile space mouse which use pin-type vibrotactile display modules and a gyroscope chip. This mouse is a new interface device which is not only an input device as an ordinary space mouse but also a tactile output device. It consists of a space mouse which use gyroscope chip and vibrotactile display modules which have been developed in our own laboratory. Lately, by development of vibrotactile display modules which have small size and consume low power, vibrotactile displays are available in small sized embedded systems such as wireless mouses or mobile devices. Also, development of new sensors like miniature size gyroscope by MEMS technology enables manufacturing of a small space mouse which can be used in the air not in a plane. The vibrotactile space mouse proposed in this paper recognizes motion of a hand using the gyroscope chip and transmits the data to PC through Bluetooth. PC application receives the data and moves pointer. Also, 2 by 3 arrays of pin-type vibrotactile actuators are mounted on the front side of the mouse where fingers of a user's hand contact, and those actuators could be used to represent various information such as gray-scale of an image or Braille patterns for visually impared persons.

• Proceedings of the KSME Conference
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• 2004.11a
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• pp.1241-1246
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• 2004

The heat flux on a chip is rapidly increasing with decreasing the size of one. It is necessary to properly cool the high heat flux chip. One of the promising cooling methods is to apply CPL heat pipes with porous materials, for example PVA, polyethylene, and powder sintered metal plate and with microchannels in the evaporator. A small scale CPL heat pipe with PVA as wick was designed and manufactured. Since the height difference between the evaporator and the condenser is a crucial parameter in the CPL heat pipes, the performance of the heat pipes depending on the parameter was investigated. The parameter is higher the performance is better. However, the improvement rate of the performance does not increase the increase rate of the height. In addition to, the parameter effect depending on heat input was investigated.

• Journal of Electrical Engineering and information Science
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• v.2 no.4
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• pp.8-13
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• 1997

This paper describes a scalable systolic synchronous memory for digital signal processing and packet switching. The systolic synchronous memory consists of the 2-D array of small memory blocks which are fully pipelined and communicated in three directions with adjacent blocks. The maximum delay of a small memory block becomes the operation speed of the chip. The array configuration is scalable for the entire memory size requested by an application. it has the initial latency of N+3 cycles with NxN array configuration. We designed an experimental 200 MHz 4Kb static RAM chip with the 4x4 array configuration of 256 SRAM blocks. It was fabricated is 0.8$\mu\textrm{m}$ twin-well single-poly double-metal CMOS technology.

• Journal of the Korean institute of surface engineering
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• v.28 no.2
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• pp.67-76
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• 1995

The microstructure of 95wt.%Pb/5wt.%Sn and 63wt.%Sn/37wt.%Pb solders for flip chip bonding process has been characterized. Solders were deposited by thermal evaporation and reflowed in the conventional furnace or by rapid thermal annealing(RTA) process. As-deposited films show columnar structure. The microstructure of furnace cooled 63Sn/37Pb solder shows typical lamellar form, but that of RTA treated solder has the structure showing an uniform dispersion of Pb-rich phase in Sn matrix. The grain size of 95Pb/5Sn solder reflowed in the furnace is about $5\mu\textrm{m}$, but the grain size of RTA treated solder is too small to be observed. The microstructure in 63Sn/37Pb solder bump shows the segregation of Pb phase in the Sn rich matrix regardless of reflowing method. The 63Sn/37Pb solder bump formed by RTA process shows more uniform microstructure. These result are related to the heat dissipation in the solder bump.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1305-1308
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• 1987

This paper presents a design of an optimized implantable biotelemetry system and the fabrication of custom CMOS LSI for implementing this system. The internal circuits of this system are fabricated on a single silicon chip with a size of $4{\times}5mm^2$. This LSI is designed and fabricated not only to get as small size and low power dissipation as possible, but also to have multiple function. Its main functions are to select one of implanted sensors and to accomplish ON - OFF power switching of an implanted battery by receiving appropriate Command signals and control signals fran external circuits. The internal system which was assembled on a bread-board using fabricated LSI chip is confirmed to work as designed. The total power dissipation of this interal system was $10.12{\mu}W$.

• Journal of IKEEE
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• v.1 no.1 s.1
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• pp.1-10
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• 1997

It is well-known that rectangular bulk-Si sensors prepared by etch or epi etch-stop micromachining technology are already in practical use today, but the conventional bulk-Si sensor shows some drawbacks such as large chip size and limited applications as silicon sensor device is to be miniaturized. We consider a circular-shape SOI(Silicon-On-Insulator) micro-cavity technology to facilitate multiple sensors on very small chip, to make device easier to package than conventional sensor like pressure sensor and to provide very high over-pressure capability. This paper demonstrates the cross-functional results for stress analyses(targeting $5{\mu}m$ deflection and 100MPa stress as maximum at various applicable pressure ranges), for finding permissible diaphragm dimension by output sensitivity, and piezoresistive sensor theory from two-type SOI structures where the double SOI structure shows the most feasible deflection and small stress at various ambient pressures. Those results can be compared with the ones of circular-shape bulk-Si based sensor$^{[17]}. The SOI micro-cavity formed the sensors is promising to integrate with calibration, gain stage and controller unit plus high current/high voltage CMOS drivers onto monolithic chip.