• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.11
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• pp.32-40
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• 2016

IEEE 802.15.4 is the one of the protocols for radio communication in a personal area network. Because of low cost and low power communication for IoT communication, it requires the highest optimization level in the implementation. Recently, the studies of location aware algorithm based on IEEE802.15.4 standard has been achieved. Location estimation is performed basically in equal consideration of reference node information and blind node information. However, an error is not calculated in this algorithm despite the fact that the coordinates of the estimated location of the blind node include an error. In this paper, we enhanced a conventual maximum likelihood estimation using weighted coefficient and implement the hardwired location aware engine for small code size and low power consumption. On the field test using test-beds, the suggested hardware based location awareness method results better accuracy by 10 percents and reduces both calculation and memory access by 30 percents, which improves the systems power consumption.

• Korean Journal of Construction Engineering and Management
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• v.10 no.4
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• pp.26-37
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• 2009

Ministry of Land, Transportation and Marine Affairs(MLTM) has implemented Construction CALS project for improving productivity of construction industry and for making construction project management efficient by responding to informatization and knowledge base society in 21st century. CALS has beeb applied successfully to projects form MLTM, however, the outcomes of Construction CALS hasn't been recognized. In addition, there is no way to find how high the level of Construction CALS is when it is compared with other SOC informatization projects. This study found out the informatiziation level of Construction CALS by using the evaluation index proposed in the former study, and by comparing with other sectors. The evaluation on the level was implemented in the three parts such as informatization infrastructure(network, hardware, standardization, data, informatization, informatization security), informatization utilization(information usage, IT performance), and informatization support(informatization goal, organization of informatization, informatization investment, informatization education), and then, this evaluation was compared with "Assessment for level of industry information system", "Assessment for level of small and midium sized industry information system", and "IICI(Informatizaion Index for the Construction Industry)". With the result from the comparison, this study produced superior factors and inferior factors for each sector. These results are expected to be useful for prioritizing budget allocation by finding out the informatization level of Construction CALS.

• Health Policy and Management
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• v.13 no.2
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• pp.67-84
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• 2003

Immunization has been one of the most effective measures preventing from infectious diseases. However, children routine vaccination rate of Korea was 68.2% and it was not higher than expected. Korean government revised the School Health Law for every primary school children to submit the vaccination certificate record from 2005. It is quite important national Infectious disease prevention policy to keep the immunizations rate high and monitor the immunizations rate continuously. To do this, National Institute of Health introduced the National Immunization Registry(NIR) Program at 2000. Objective : The aims of this study was to evaluate the Immunization Registry program which has been implementing since 2000 at the Public Health Centers(PHC). Methods : The mail survey was done from November 2001 to January 2002. 169 (69%) Public Health Centers among 244 PHC were responded. Results : The respondents of PHC sud the Immunization Registry(IR) program had reduced the workload (18.5%). 69.2% said they inputted the immunization data into the IR program after the shots were given. 86.5% said they hadn´t checked or retrieved the children lists who had missed the scheduled immunization. Only 17.2% said the speed of internet for the R program was good. It showed that 20% of respondents hadn´t written down documents, records on immunization any more. Even there were a lot of negative results, the respondents of PHC thought that the IR program was effective. They especially agreed that the IR program could make the job accurate (81.5%), convenient (71.3%), and reduced the chances of making mistakes (71.3%), increase the service quality (78.5%). And they were well adapting the job process of the IR (79.63%). Bivariate analysis showed that the software program was the important determinants of IR success. The only Bit Computer software program has been evaluated to be less satisfactory than the Integrated (Posdata operating system + Bit software) program. Other variables, such as age, duration of present job, and location of PHC (metropolitan, small city, rural area) were not significantly related. Conclusion : It seemed that the success of NIR might depend on the software program. Because Integrated program, which has been developed from 1994, include not only the general operating and management program for PHC but also IR program. It was natural to prefer Integrated program to Bit software program. So we can suggest that it is essential for the NIR to be successful that not only the immunization software program but also hardware equipments and public health information system should be further improved.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.3
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• pp.178-192
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• 2006

The buffer overflow attack is the single most dominant and lethal form of security exploits as evidenced by recent worm outbreaks such as Code Red and SQL Stammer. In this paper, we propose microarchitectural techniques that can detect and recover from such malicious code attacks. The idea is that the buffer overflow attacks usually exhibit abnormal behaviors in the system. This kind of unusual signs can be easily detected by checking the safety of memory references at runtime, avoiding the potential data or control corruptions made by such attacks. Both the hardware cost and the performance penalty of enforcing the safety guards are negligible. In addition, we propose a more aggressive technique called corruption recovery buffer (CRB), which can further increase the level of security. Combined with the safety guards, the CRB can be used to save suspicious writes made by an attack and can restore the original architecture state before the attack. By performing detailed execution-driven simulations on the programs selected from SPEC CPU2000 benchmark, we evaluate the effectiveness of the proposed microarchitectural techniques. Experimental data shows that enforcing a single safety guard can reduce the number of system failures substantially by protecting the stack against return address corruptions made by the attacks. Furthermore, a small 1KB CRB can nullify additional data corruptions made by stack smashing attacks with only less than 2% performance penalty.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.3
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• pp.699-707
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• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.7
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• pp.1-8
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• 2018

This paper describes new communication methods for transmitting torque commands between the vehicle controller that determines the amount of power generation in a range-extended electric vehicle and the engine controller that performs it. Generally, vehicles use CAN communication, but in this case, the hardware and software of the existing engine controller must be modified. For this reason, it is not easy to apply CAN communication to small and medium sized automotive reorganize companies. Therefore, this research presents a pin-pin communication method for applying the existing mass produced engine controller to range-extended electric vehicles. The pin-pin communication method converts the driver's demand torque control map inside an mass produced engine controller into a virtual accelerator opening position according to the target speed and target torque of the engine, and converts this to a voltage signal for the existing mass produced engine controller to recognize it. The virtual accelerator opening positions are mounted in the form of a control map in the vehicle controller through the reverse conversion process in an offline environment and are determined by the engine generating power requirements and engine optimal operating point algorithm. These algorithms and signal conversion circuits for engine torque transmission have been mounted on the vehicle controller to conduct the virtual accelerator opening position conversion process according to the engine target torque and to establish the virtual accelerator voltage signal using the signal converter.

• Journal of KIISE:Computing Practices and Letters
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• v.12 no.6
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• pp.367-378
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• 2006

A mobile phone has became as a payment tool in e-commerce and on-line banking areas. This trend of a payment system using various types of mobile devices is rapidly growing, especially in the Internet transaction and small-money payment. Hence, there will be a need to define its standard for secure and safe payment technology. In this thesis, we consider the service types of the current mobile payments and the authentication method, investigate the disadvantages, problems and their solutions for smart and secure payment. Also, we propose a novel authentication method which is easily adopted without modification and addition of the existed mobile hardware platform. Also, we present a simple implementation as a demonstration version. Based on virtual machine (VM) approach, the proposed model is to use a pseudo-random number which is confirmed by the VM in a user's mobile phone and then is sent to the authentication site. This is more secure and safe rather than use of a random number received by the previous SMS. For this payment operation, a user should register the serial number at the first step after downloading the VM software, by which can prevent the illegal payment use by a mobile copy-phone. Compared with the previous SMS approach, the proposed method can reduce the amount of packet size to 30% as well as the time. Therefore, the VM-based method is superior to the previous approaches in the viewpoint of security, packet size and transaction time.

• Journal of KIISE:Information Networking
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• v.28 no.2
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• pp.262-276
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• 2001

Recently much research for developing forwarding table that support fast router without employing both special hardware and new protocols. This article introduces a new forwarding data structure based on the software to enable forwarding lookup to be penormed at giga-bit speed. The forwarding table is known as a bottleneck of the routers penormance due to its high complexity proportional to the forwarding table size. The recent research that based on the software uses a Patricia trie and its variants. and also uses a hash function with prefix length key and others. The proposed forwarding table structure construct a forwarding table by the bit stream array in which it constructs trie from routing table prefix entries and it represents each pointer pointing the child node and the associated forwarding table entry with one bit The trie structure and routing prefix pointer need a large memory when representing those by linked-list or array. but in the proposed data structure, the needed memory size is small enough since it represents information with one bit. Additionally, by use a lookup method that start searching at desired middle level we can shorten the search path. The introduced data structure. called bit-map trie shows that we can implement a fast forwarding engine on the conventional Pentium processor by reducing the backbone routing table fits into Level 2 cache of Pentium II processor and shortens the searching path. Our experiments to evaluate the performance of proposed method show that this bit-map trie accomplishes 5.7 million lookups per second.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• Journal of the Korean GEO-environmental Society
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• v.16 no.3
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• pp.41-48
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• 2015

Several sensor systems are used to estimate and predict the slope behaviors, however though slope sensing systems are much up-to-dated compared to before, they are mainly focused on the hardware developing. It means the analyzing software is deficient to apply the examining slope behavior for slope stability. In real case, slope behavior shows the 3-dimensional movement and failure; however the modeling methods for 3-D behavior are more difficult and need more variables. 1-D analysis shows only the length variation, however the real slope makes the 3-D behaviors. To fix the 3-D space coordinate, three values should be determined such as length, horizontal angle and vertical angle. Therefore if the 3-D coordinate system were composed by the points considered of two directions and length, the 3-D space could be separated into horizontal plane and vertical plane. The data from DY-slope in Chungbuk province was analyzed to the developed 3-D coordinate system. It is concluded from the results of 3-D analysis, the slope is generally moving to transverse direction, also the displacements are happening to road and vertical direction at the same time. Presently, the accumulated displacement between sensing points shows small value within 4.3 cm, and the displacements of all sensing points show the similar directions and magnitudes.