• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.195-202
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• 2004

This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

• Microbiology and Biotechnology Letters
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• v.40 no.4
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• pp.414-418
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• 2012

The quantity of research on microbial fuel cells has been rapidly increasing. Microbial fuel cells are unique in their ability to utilize microorganisms and to generate electricity from sewage, pig excrement, and other wastewaters which include organic matter. This system can directly produce electrical energy without an inefficient energy conversion step. However, with MFCs maximum power production is limited by several factors such as activation losses, ohmic losses, and mass transfer losses in cathodes. Therefore, electron acceptors such as nitrate and ferric ion in the cathodes were utilized to improve the cathode reaction rate because the cathode reaction is very important for electricity production. When 100 mM nitrate as an electron acceptor was fed into cathodes, the current in single-cathode and dual-cathode MFCs was noted as $3.24{\pm}0.06$ mA and $4.41{\pm}0.08$ mA, respectively. These values were similar to when air-saturated water was fed into the cathodes. One hundred mM nitrate as an electron acceptor in the cathode compartments did not affect an increase in current generation. However, when ferric ion was used as an electron acceptor the current increased by $6.90{\pm}0.36$ mA and $6.67{\pm}0.33$ mA, in the single-cathode and dual-cathode microbial fuel cells, respectively. These values, in single-cathode and dual-cathode microbial fuel cells, represent an increase of 67.1% and 17.6%, respectively. Furthermore, when supplied with ferric ion without air, the current was higher than that of only air-saturated water. In this study, we attempted to reveal an inexpensive and readily available electron acceptor which can replace platinum in cathodes to improve current generation by increasing the cathode reaction rate.

• Bulletin of the Korean Chemical Society
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• v.33 no.9
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• pp.3061-3070
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• 2012

Novel 2-hexylthieno[3,2-b]thiophene-containing conjugated molecules have been synthesized via a reduction reaction using tin chloride in an acidic medium. They exhibited good solubility in common organic solvents and good self-film and crystal-forming properties. The single-crystalline objects were fabricated by a solvent slow diffusion process and then were employed for fabricating field-effect transistors (FETs) along with thinfilm transistors (TFTs). TFTs made of 5 and 6 exhibited carrier mobility as high as 0.10-0.15 $cm^2V^{-1}s^{-1}$. The single-crystal-based FET made of 6 showed 0.70 $cm^2V^{-1}s^{-1}$ which was relatively higher than that of the 5-based FET (${\mu}=0.23cm^2V^{-1}s^{-1}$). In addition, we fabricated organic photovoltaic (OPV) cells with new 2-hexylthieno [3,2-b]thiophene-containing conjugated molecules and methanofullerene [6,6]-phenyl C61-butyric acid methyl ester ($PC_{61}BM$) without thermal annealing. The ternary system for a bulk heterojunction (BHJ) OPV cell was elaborated using $PC_{61}BM$ and two p-type conjugated molecules such as 5 and 7 for modulating the molecular energy levels. As a result, the OPV cell containing 5, 7, and $PC_{61}BM$ had improved results with an open-circuit voltage of 0.90 V, a short-circuit current density of 2.83 $mA/cm^2$, and a fill factor of 0.31, offering an overall power conversion efficiency (PCE) of 0.78%, which was larger than those of the devices made of only molecule 5 (${\eta}$~0.67%) or 7 (${\eta}$~0.46%) with $PC_{61}BM$ under identical weight compositions.

• Journal of Broadcast Engineering
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• v.12 no.1 s.34
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• pp.11-27
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• 2007

T-DMB(Terrestrial-Digital Multimedia Broadcasting) for portable and mobile broadcasting service was officially launched in the metropolitan area of Korea in December 2005. The development of interactive data services and the expansion of T-DMB network have been now progressed, and the regional T-DMB broadcasters will be selected in the near future. Although it is important to evaluate service area and reduce a fringe area for optimizing RF coverage of T-DMB, there was no professional system to support those works, and therefore lots of resources in budget, manpower and time were required. The measurement considering characteristics of SFN(Single Frequency Network) is essential in the implementation of T-DMB network which needs to control synchronization, spacing and output power of transmitters. In addition, mobile measurement, enough measured parameters for many-sided analysis of reception quality, efficient management of enormous measured data and representation of measured results on the electronic map are also important in evaluating service area. In this paper, we derived requirements for a new measurement system in T-DMB by considering the above details, and we proposed and developed an integrated measurement and analysis system. The developed system was applied to the implementation of T-DMB network of KBS and field tests, and it proved its efficiency and accuracy in result.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.83-89
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• 2006

This paper describes the design of I/Q channel 12bit Digital-to-Analog Converter(DAC) which shows the conversion rate of 120MHz and the power supply of 3.3V with 0.35um CMOS n-well 1-poly 4-metal process for advanced wireless transceiver. The proposed DAC utilizes 4-bit thermometer decoder with 3 stages for minimum glitch energy and linearity error. Also, using a optimized 4bit thermometer decoder for the decrement of the chip area. Integral nonlinearity(INL) of ${\pm}1.6LSB$ and differential nonlinearity(DNL) of ${\pm}1.3LSB$ have been measured. In single tone test, the ENOB of the proposed 12bit DAC is 10.5bit and SFDR of 73dB(@ Fs=120MHz, Fin=1MHz) is measured, respectively. Dual-tone test SFDR is 61 dB (@ Fs=100MHz, Fin=1.5MHz, 2MHz). Glitch energy of 31 pV.s is measured. The converter consumes a total of 105mW from 3.3-V power supply.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.3
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• pp.29-34
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• 2019

Silicon carbide is considered to be a potentially useful material for high-temperature electronic devices, as its large energy band gap and the p-type and/or n-type conduction can be controlled by impurity doping. Particularly, electric conductivity of porous n-type SiC semiconductors fabricated from ${\beta}-SiC$ powder at $2000^{\circ}C$ in $N_2$ atmosphere was comparable to or even larger than the reported values of SiC single crystals in the temperature region of $800^{\circ}C$ to $1000^{\circ}C$, while thermal conductivity was kept as low as 1/10 to 1/30 of that for a dense SiC ceramics. In this work, for the purpose of decreasing sintering temperature, it was attempted to fabricate porous reaction-sintered bodies at low temperatures ($1400-1600^{\circ}C$) by thermal decomposition of polycarbosilane (PCS) impregnated in n-type ${\beta}-SiC$ powder. The repetition of the impregnation and sintering process ($N_2$ atmosphere, $1600^{\circ}C$, 3h) resulted in only a slight increase in the relative density but in a great improvement in the Seebeck coefficient and electrical conductivity. However the power factor which reflects the thermoelectric conversion efficiency of the present work is 1 to 2 orders of magnitude lower than that of the porous SiC semiconductors fabricated by conventional sintering at high temperature, it can be stated that thermoelectric properties of SiC semiconductors fabricated by the present reaction-sintering process could be further improved by precise control of microstructure and carrier density.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.154.2-154.2
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• 2016

In this work, we introduce a solution-processed CdS interlayer for use in inverted bulk heterojunction (BHJ) solar cells, and compare this material to a series of standard organic and inorganic cathode interlayers. Different combinations of solution-processed CdS, ZnO and conjugated polyelectrolyte (CPE) layers were compared as cathode interlayers on ITO substrates to construct inverted solar cells based on $PTB7:PC_{71}BM$ and a $P3HT:PC_{61}BM$ as photoactive layers. Introduction of a CdS interlayer significantly improved the power conversion efficiency (PCE) of inverted $PTB7:PC_{71}BM$ devices from 2.0% to 4.9%, however, this efficiency was still fairly low compared to benchmark ZnO or CPE interlayers due to a low open circuit voltage ($V_{OC}$), stemming from the deep conduction band energy of CdS. The $V_{OC}$ was greatly improved by introducing an interfacial dipole (CPE) layer on top of the CdS layer, yielding outstanding diode characteristics and a PCE of 6.8%. The best performing interlayer, however, was a single CPE layer alone, which yielded a $V_{OC}$ of 0.727 V, a FF of 63.2%, and a PCE of 7.89%. Using $P3HT:PC_{61}BM$ as an active layer, similar trends were observed. Solar cells without the cathode interlayer yielded a PCE of 0.46% with a poor $V_{OC}$ of 0.197 V and FF of 34.3%. In contrast, the use of hybrid ZnO/CPE layer as the cathode interlayer considerably improved the $V_{OC}$ of 0.599 V and FF of 53.3%, resulting the PCE of 2.99%. Our results indicate that the CdS layer yields excellent diode characteristics, however, performs slightly worse than benchmark ZnO and CPE layers in solar cell devices due to parasitic absorption below 550 nm. These results suggest that the hybrid inorganic/organic interlayer materials are promising candidates as cathode interlayers for high efficiency inverted solar cells through the modification of interface contacts.

• Journal of the Korean Vacuum Society
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• v.16 no.3
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• pp.161-166
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• 2007

Photovoltaic (PV) technology permits the transformation of solar light directly into electricity. For the last five years, the photovoltaic sector has experienced one of the highest growth rates worldwide (over 30% in 2006) and for the next 20 years, the average production growth rate is estimated to be between 27% and 34% annually. Currently the cost of electricity produced using photovoltaic technology is above that for traditional energy sources, but this is expected to fall with technological progress and more efficient production processes. A large scale production of solar grade silicon material of high purity could supply the world demand at a reasonably lower cost. A shift from crystalline silicon to thin film is expected in the future. The technical limit for the conversion efficiency is about 30%. It is assumed that in 2030 thin films will have a major market share (90%) and the share of crystalline cells will have decreased to 10%. Our research at Sungkyunkwan University of South Korea is confined to crystalline silicon solar cell technology. We aim to develop a technology for low cost production of high efficiency silicon solar cell. We have successfully fabricated silicon solar cells of efficiency more than 16% starting with multicrystalline wafers and that of efficiency more than 17% on single crystalline wafers with screen printing metallization. The process of transformation from the first generation to second generation solar cell should be geared up with the entry of new approaches but still silicon seems to remain as the major material for solar cells for many years to come. Local barriers to the implementation of this technology may also keep continuing up to year 2010 and by that time the cost of the solar cell generated power is expected to be 60 cent per watt. Photovoltaic source could establish itself as a clean and sustainable energy alternate to the ever depleting and polluting non-renewable energy resource.

• Journal of the Korean Vacuum Society
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• v.21 no.1
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• pp.29-35
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• 2012

The Hydrogenated silicon nitride (SiNx:H) using plasma enhanced chemical vapor deposition is widely used in photovoltaic industry as an antireflection coating and passivation layer. In the high temperature firing process, the $SiN_x:H$ film should not change the properties for its use as high quality surface layer in crystalline silicon solar cells. Initially PECVD-$SiN_x:H$ film trends were investigated by varying the deposition parameters (temperature, electrode gap, RF power, gas flow rate etc.) to optimize the process parameter conditions. Then by varying gas ratios ($NH_3/SiH_4$), the hydrogenated silicon nitride films were analyzed for its optical, electrical, chemical and surface passivation properties. The $SiN_x:H$ films of refractive indices 1.90~2.20 were obtained. The film deposited with the gas ratio of 3.6 (Refractive index=1.98) showed the best properties in after firing process condition. The single crystalline silicon solar cells fabricated according to optimized gas ratio (R=3.6) condition on large area substrate of size $156{\times}156mm$ (Pseudo square) was found to have the conversion efficiency as high as 17.2%. Optimized hydrogenated silicon nitride surface layer and high efficiency crystalline silicon solar cells fabrication sequence has also been explained in this study.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.62-68
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• 2010

This work proposes a 10b 100MS/s DAC based on a segmented local matching technique primarily for small chip area. The proposed DAC employing a segmented current-steering structure shows the required high linearity even with the small number of devices and demonstrates a fast settling behavior at resistive loads. The proposed segmented local matching technique reduces the number of current cells to be matched and the size of MOS transistors while a double-cascode topology of current cells achieves a high output impedance even with minimum sized devices. The prototype DAC implemented in a 0.13um CMOS technology occupies a die area of $0.13mm^2$ and drives a $50{\Omega}$ load resistor with a full-scale single output voltage of $1.0V_{p-p}$ at a 3.3V power supply. The measured DNL and INL are within 0.73LSB and 0.76LSB, respectively. The maximum measured SFDR is 58.6dB at a 100MS/s conversion rate.