• JSTS:Journal of Semiconductor Technology and Science
• /
• v.12 no.4
• /
• pp.418-425
• /
• 2012

In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit pre-computation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weight-column code during the write operation and is designed by replacing 0's with 1's at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the odd-weight- column code, the implementation based on the proposed SEC-DED code with check bit pre-computation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.13 no.4
• /
• pp.721-728
• /
• 2018

This paper introduces various linear block error correction code and compares performances of the correction circuits. As the risk of errors due to power noise has increased, ECC(: Error Correction Code) has been introduced to prevent the bit error. There are two representatives of ECC structures which are SEC-DED(: Single Error Correction Double Error Detection) and SEC-DED-DAEC(: Double Adjacent Error Correction). According to simulation results, the SEC-DED circuit has advantages of small area and short delay time compared to SEC-DED-DAEC circuits. In case of SED-DED-DAEC, there is no big difference between Dutta's and Pedro's from performance point of view. Therefore, Pedro's code is more efficient than Dutta' code since the correction rate of Pedro's code is higher than that of Dutta's code.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.26 no.10
• /
• pp.1559-1562
• /
• 2022

As electronic devices technology scales down into the deep-submicron to achieve high-density, low power and high performance integrated circuits, multiple bit upsets by soft errors have become a major threat to on-chip memory systems. To address the soft error problem, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not troubleshoot mis-correction problem. We propose the SEC-DED_DAEC code with without mis-correction. The decoder for proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the decoder can be employed on-chip memory system.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.17 no.1
• /
• pp.31-40
• /
• 2022

This paper proposes an augmented QSBC(Quantum Short-Block Code) that preserves the function of the existing QSBC and adds a single bit-flip error correction function due to Pauli X and Y errors. The augmented QSBC provides the diagnosis and automatic correction of a single Pauli X error by inserting additional auxiliary qubits and Toffoli gates as many as the number of information words into the existing QSBC. In this paper, the general expansion method of the augmented QSBC using seed vector and the realization method of the Toffoli gate of the single bit-flip error automatic correction function reflecting the scalability are also presented. The augmented QSBC proposed in this paper has a trade-off with a coding rate of at least 1/3 and at most 1/2 due to the insertion of auxiliary qubits.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.26 no.11
• /
• pp.1747-1750
• /
• 2022

As shrinking the semiconductor process into the deep sub-micron to achieve high-density, low power and high performance integrated circuits, MBU (multiple bit upset) by soft errors is one of the major challenge of on-chip memory systems. To address the MBU, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not resolve mis-correction. We propose the SEC-DED-DAEC-TAED(triple adjacent error detection) code without mis-corrections. The generated H-matrix by the proposed heuristic algorithm to accomplish the proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the 2-stage pipelined decoder can be employed on-chip memory system.

• The Korean Journal of Applied Statistics
• /
• v.29 no.1
• /
• pp.75-83
• /
• 2016

We propose methodology to analyze the dynamic mechanisms of financial market contagion under market integration using a biological contagion analytical approach. We employ U-statistic to measure market integration, and a dynamic model based on an error correction mechanism (single equation error correction model) and latent factor model to examine market contagion. We also use quantile regression and Wald-Wolfowitz runs test to test market contagion. This methodology is designed to effectively handle heteroscedasticity and correlated errors. Our simulation results show that the single equation error correction model fits well with the linear regression model with a stationary predictor and correlated errors.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.7A
• /
• pp.712-718
• /
• 2004

We report 1.6 Tb/s (160${\times}$10 Gb/s) WDM transmission over 2,000 km of single mode fiber using distributed hybrid(distributed Raman amplifier＋Erbium-doped fiber amplifier) optical amplifiers. After transmission over 2,000 km of single mode fiber, average optical signal to noise ratios of C/L-band were 20.5 dB, 21.9 dB, respectively. The minimum Q-factors of each band were 14.65 dB (BER=5.8e-8) in C-band, 13.75 dB (BER=5.0e-7) in L-band without forward error correction. We performed 1.6 Tb/s error-free transmission over 2,000 km of single mode fiber using Reed-Solomon (255, 239) forward error correction code.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.59 no.2
• /
• pp.417-422
• /
• 2010

When memory devices are exposed to space environments, they suffer various effects such as SEU(Single Event Upset). Memory systems for space applications are generally equipped with error detection and correction(EDAC) logics against SEUs. In this paper, several error detection and correction codes - RS(10,8) code, (7,4) Hamming code and (16,8) code - are analyzed and compared with each other. Each code is implemented using VHDL and its performances(encoding/decoding speed, required memory size) are compared. Also the failure probability equation of each EDAC code is derived, and the probability value is analyzed for various occurrence rates of SEUs which the STSAT-3 possibly suffers. Finally, the EDAC algorithm for STSAT-3 is determined based on the comparison results.

• Journal of Positioning, Navigation, and Timing
• /
• v.12 no.2
• /
• pp.121-128
• /
• 2023

When calculating the user's position using satellite signals, the signals originating from the satellite pass through the ionosphere and troposphere to the user. In particular, the ionosphere delay error that occurs when passing through the ionosphere delays when the signal is transmitted, generating a pseudorange error and position error at a large rate. Therefore, to improve position accuracy, it is essential to correct the ionosphere layer error. In a receiver capable of receiving dual frequency, the ionosphere error can be eliminated through a double difference, but in a single frequency receiver, an ionosphere correction model transmitted from a Global Navigation Satellite System (GNSS) satellite is used. The popularly used Klobuchar model is designed to improve performance globally. As such, it does not perform perfectly in the Korea region. In this paper, the characteristics of the delay in the ionosphere in the Korean region are identified through an analysis of 10 years of data, and an improved ionosphere correction model for the Korean region is presented using the widely employed Klobuchar model. Through the proposed model, vertical position error can be improved by up to 40% relative to the original Klobuchar model in the Korea region.

• ETRI Journal
• /
• v.30 no.6
• /
• pp.799-806
• /
• 2008

In this paper, a new design for an error correcting code (ECC) is proposed. The design is aimed to build an ECC circuitry with minimal power consumption. The genetic algorithm equipped with the symbiotic mechanism is used to design a power-efficient ECC which provides single-error correction and double-error detection (SEC-DED). We formulate the selection of the parity check matrix into a collection of individual and specialized optimization problems and propose a symbiotic evolution method to search for an ECC with minimal power consumption. Finally, we conduct simulations to demonstrate the effectiveness of the proposed method.