• Title/Summary/Keyword: single carrier modulation

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Two-Dimensional Pilot Symbol Assisted Channel Estimation for OFDM Systems over Frequency Selective Rayleigh Fading Channel (주파수 선택적 레일리 페이딩 채널에서 OFDM 시스템을 위한 2-D PSA에 의한 채널 추정)

  • 이병로
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2001.10a
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    • pp.336-340
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    • 2001
  • In this paper we analyze the performance of 2-D PSAM for wireless OFDM systems. We apply the analysis of single-carrier PSAM to the 2-D time-frequency lattice of OFDM. To estimate channel fading, we use interpolation filter which minimizes the average power of error as compensation method and analyze the affects on the system performance of the pilot symbol pattern on the 2-D tine-frequency lattice. Finally according to the CP and the Doppler frequency, we analyze the performance of 2-D PSA-16QAM for OFDM systems over frequency selective Rayleigh fading channel model.

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Continuous Multiple Phase Differential Detection of Trellis-coded MDPSK-OFDM (연속적인 다중 위상 검출을 이용한 트렐리스 부호화된 MDPSK-OFDM)

  • 안필승;김한종;김종일
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2002.05a
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    • pp.568-573
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    • 2002
  • In this paper, the Viterbi decoder containing new branch metrics of the squared Euclidean distance with multiple order phase differences is introduced in order to improve the bit error rate (BER) in the differential detection of the trellis-coded MDPSK-OFDM. The proposed Viterbi decoder is conceptually same as the Continuous multiple phase differential detection method that uses the branch metric with multiple phase differences. Also, we describe the Viterbi algorithm in order to use this branch metrics. Our study shows that such a Viterbi decoder improves BER performance without sacrificing bandwidth and power efficiency Also. the proposed algorithm ran be used in the single carrier modulation.

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A New Random SPWM Technique for AC-AC Converter-Based WECS

  • Singh, Navdeep;Agarwal, Vineeta
    • Journal of Power Electronics
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    • v.15 no.4
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    • pp.939-950
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    • 2015
  • A single-stage AC-AC converter has been designed for a wind energy conversion system (WECS) that eliminates multistage operation and DC-link filter elements, thus resolving size, weight, and reliability issues. A simple switching strategy is used to control the switches that changes the variable-frequency AC output of an electrical generator to a constant-frequency supply to feed into a distributed electrical load/grid. In addition, a modified random sinusoidal pulse width modulation (RSPWM) technique has been developed for the designed converter to make the overall system more efficient by increasing generating power capacity and reducing the effects of inter-harmonics and sub-harmonics generated in the WECS. The technique uses carrier and reference waves of variable switching frequency to calculate the firing angles of the switches of the converter so that the three-phase output voltage of the converter is very close to a sine wave with reduced THD. A comparison of the performance of the proposed RSPWM technique with the conventional SPWM demonstrated that the power generated by a turbine in the proposed approximately increased by 5% to 10% and THD reduces by 40% both in voltage and current with respect to conventional SPWM.

Photonic Generation of Frequency-tripling Vector Signal Based on Balanced Detection without Precoding or Optical Filter

  • Qu, Kun;Zhao, Shanghong;Li, Xuan;Zhu, Zihang;Tan, Qinggui
    • Current Optics and Photonics
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    • v.2 no.2
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    • pp.134-139
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    • 2018
  • A novel approach for frequency-tripling vector signal generation via balanced detection without precoding and optical filter is proposed. The scheme is mainly utilizing an integrated dual-polarization quadrature phase shift keying (DPQPSK) modulator. In the DPQPSK modulator, one QPSK modulator is driven by an RF signal to generate high-order optical sidebands, while the other QPSK modulator is modulated by I/Q data streams to produce baseband vector signal as an optical carrier. After that, a frequency-tripling 16-quadrature-amplitude-modulation (16QAM) vector millimeter-wave (mm-wave) signal can be obtained by balanced detection. The proposed scheme can reduce the complexity of transmitter digital signal processing. The results show that, a 4 Gbaud baseband 16QAM vector signal can be generated at 30 GHz by frequency-tripling. After 10 km single-mode fiber (SMF) transmission, the constellation and eye diagrams of the generated vector signal perform well and a bit-error-rate (BER) below than 1e-3 can be achieved.

Implementation of Low Complexity FFT, ADC and DAC Blocks of an OFDM Transmitter Receiver Using Verilog

  • Joshi, Alok;Gupta, Dewansh Aditya;Jaipuriyar, Pravriti
    • Journal of Information Processing Systems
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    • v.15 no.3
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    • pp.670-681
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    • 2019
  • Orthogonal frequency division multiplexing (OFDM) is a system which is used to encode data using multiple carriers instead of the traditional single carrier system. This method improves the spectral efficiency (optimum use of bandwidth). It also lessens the effect of fading and intersymbol interference (ISI). In 1995, digital audio broadcast (DAB) adopted OFDM as the first standard using OFDM. Later in 1997, it was adopted for digital video broadcast (DVB). Currently, it has been adopted for WiMAX and LTE standards. In this project, a Verilog design is employed to implement an OFDM transmitter (DAC block) and receiver (FFT and ADC block). Generally, OFDM uses FFT and IFFT for modulation and demodulation. In this paper, 16-point FFT decimation-in-frequency (DIF) with the radix-2 algorithm and direct summation method have been analyzed. ADC and DAC in OFDM are used for conversion of the signal from analog to digital or vice-versa has also been analyzed. All the designs are simulated using Verilog on ModelSim simulator. The result generated from the FFT block after Verilog simulation has also been verified with MATLAB.

A 1.485 Gbps Wireless Video Signal Transmission System at 240 GHz (240 GHz, 1.485 Gbps 비디오신호 무선 전송 시스템)

  • Lee, Won-Hui;Chung, Tae-Jin
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.10 no.4
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    • pp.105-113
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    • 2010
  • In this paper, a 1.485 Gbps video signal transmission system using the carrier frequency of 240 GHz band was designed and simulated. The sub-harmonic mixer based on Schottky barrier diode was simulated in the transmitter and receiver. Both of heterodyne and direct detection receivers were simulated for each performance analysis. The ASK modulation was used in the transmitter and the envelop detection method was used in the receiver. The transmitter simulation results showed that the RF output power was -11.4 dBm($73{\mu}W$), when the IF input power was -3 dBm(0.5 mW) at the LO power of 7 dBm(5 mW) in sub-harmonic mixer, which corresponds to SSB(Single Side Band) conversion loss of 8.4 dB. This value is similar to the conversion loss of 8.0 dB(SSB) of VDI's commercial model WR3.4SHM(220~325 GHz) at 240 GHz. The combined transmitter and receiver simulation results showed that the recovered signal waveforms were in good agreement to the transmitted 1.485 Gbps NRZ signal.

Single Phase 5-level Inverter with DC-link Switches (DC링크 스위치를 갖는 단상 5레벨 인버터)

  • Choi, Young-Tae;Sun, Ho-Dong;Park, Min-Young;Kim, Heung-Geun;Chun, Tea-Won;Nho, Eui-Cheol
    • The Transactions of the Korean Institute of Power Electronics
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    • v.16 no.3
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    • pp.283-292
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    • 2011
  • This paper proposed a new multi-level inverter topology based on a H-bridge with two switches and two diodes connected to the DC-link. The output voltage of the proposed topology is quite closer to a sinusoidal waveform compared with a typical single phase inverter. The proposed multi-level inverter is applicable to a power conditioning system for renewable energy sources, and it can be also used as a building block of a cascaded multi-level inverter for a high voltage application. In case of conventional H-bridge type or NPC type multi-level inverter, 8 controllable switches are used to obtain a 5 level output voltage, but the proposed multi-level inverter requires only 6 controllable switches. Thus the circuit configuration is quite simple, reliable and cost-effective implementation is possible. The efficiency can be improved owing to the reduction of the switching loss. A new PWM method based on POD modulation is suggested which requires only one carrier signal. The switching sequence to make the capacitor voltage balanced is also considered. The feasibility is studied through simulation and experiment.

DFT-based Channel Estimation Scheme for Sidelink in D2D Communication (D2D 통신에서 사이드링크를 위한 DFT 기반 채널 추정 기법)

  • Moon, Sangmi;Chu, Myeonghun;Kim, Hanjong;Kim, Daejin;Kim, Cheolsung;Hwang, Intae
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.12
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    • pp.22-31
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    • 2015
  • Recently, 3rd Generation Partnership Project (3GPP) has developed device-to-device (D2D) communication to cope with the explosively increasing mobile data traffic. The D2D communication uses sidelink based on single carrier-frequency division multiple access (SC-FMDA) due to its low peak-to-average power ratio (PAPR). In addition, demodulation reference signal (DMRS) is designed to support multiple input multiple output (MIMO). In this paper, we propose the DFT-based channel estimation scheme for sidelink in D2D communication. The proposed scheme uses the 2-Dimensional Minimum Mean Square Error (2-D MMSE) interpolation scheme for the user moving at a high speed. We perform the system level simulation based on 20MHz bandwidth of 3GPP LTE-Advanced system. Simulation results show that the proposed channel estimation scheme can improve signal-to-interference-plus-noise ratio (SINR), throughput and spectral efficiency of conventional scheme.

A Design of Memory-efficient 2k/8k FFT/IFFT Processor using R4SDF/R4SDC Hybrid Structure (R4SDF/R4SDC Hybrid 구조를 이용한 메모리 효율적인 2k/8k FFT/IFFT 프로세서 설계)

  • 신경욱
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.2
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    • pp.430-439
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    • 2004
  • This paper describes a design of 8192/2048-point FFT/IFFT processor (CFFT8k2k), which performs multi-carrier modulation/demodulation in OFDM-based DVB-T receiver. Since a large size FFT requires a large buffer memory, two design techniques are considered to achieve memory-efficient implementation of 8192-point FFT/IFFT. A hybrid structure, which is composed of radix-4 single-path delay feedback (R4SDF) and radix-4 single-path delay commutator (R4SDC), reduces its memory by 20% compared to R4SDC structure. In addition, a memory reduction of about 24% is achieved by a novel two-step convergent block floating-point scaling. As a result, it requires only 57% of memory used in conventional design, reducing chip area and power consumption. The CFFT8k2k core is designed in Verilog-HDL, and has about 102,000 Bates, RAM of 292k bits, and ROM of 39k bits. Using gate-level netlist with SDF which is synthesized using a $0.25-{\um}m$ CMOS library, timing simulation show that it can safely operate with 50-MHz clock at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. The functionality of the core is fully verified by FPGA implementation, and the average SQNR of 60-㏈ is achieved.

Performance Analysis on DMB System with PAPR Reduction Techniques (PAPR 저감기법을 적용한 DMB 시스템의 성능분석)

  • 정영호;함영권;김환우
    • Journal of Broadcast Engineering
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    • v.8 no.3
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    • pp.238-249
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    • 2003
  • Eureka 147 DAB system based on the orthogonal frequency division multiplexing (OFDM) was adopted as the transmission scheme for terrestrial digital multimedia broadcasting (DMB) system in Korea. The OFDM has several advantages comparing to the single carrier modulation. However, its high Peak-to-average power ratio (PAPR) increases the complexity of the D/A and A/D converters and reduces the efficiency of the high power amplifier To reduce the high PAPR of OFDM, various techniques such as clipping, peak windowing, companding, selected mapping (SLM), Partial transmit sequences (PTS), etc. have been proposed. In this paper, we propose modified configurations of SLM and PTS for effective implementation and evaluate the performance on the PAPR reduction of DMB system. The simulation results show that the modified SLM (MSLM) has merits in reducing the amount of computation and hardware complexity due to the reduction of the number of vector $P^{(U)}$, while satisfying the same performance and maintaining the same required bits (RB) for side information. With the same amount of computation and the same RB, the modified PTS (MPTS) is also shown to be better than PTS in the performance of PAPR reduction.