• Proceedings of the International Microelectronics And Packaging Society Conference
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• 1999.11a
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• pp.33-36
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• 1999

In this paper, we proposed a simultaneous switching noise(SSN) reduction technique in muti-layer beards(MLB) for high-speed digital applications and analyzed them using the Finite Difference Time Domain(FDTD) method. The new method by conductive dielectric substrates reduces SSN couplings and resonances, significantly, which cause series malfunctions in the modem high-speed digital applications.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.4
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• pp.9-14
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• 1999

In this paper, we proposed a simultaneous switching noise (SSN) reduction technique in multi-layer boards (MLB) for high-speed digital applications and analyzed it using the Finite Difference Time Domain (FDTD) method. The new structure using conductive dielectric substrates is effective for the reduction of SSN couplings and resonances. The uniform insertion of the conducive layer reduced the SSN coupling and resonance by 85% and the partial insertion only around the edges reduced by 55% respectively.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.389-392
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• 1999

It is essential to estimate an effective inductance in a ground plane of muliti-layer IC package system in order to determine the simultaneous switching noise of the package. A new method to estimate the effective ground inductance in multi-layer IC package is presented. With the estimated ground plane inductance values, maximum switching noise variations according to the number of simultaneously switching drivers are investigated by developing a new SSN model. These results are verified by performing HSPICE simulation with the 0.35${\mu}{\textrm}{m}$ CMOS technology.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.11
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• pp.6565-6575
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• 2014

Hamilton's Markov-switching model [5] was extended to the simultaneous equations model. A framework for an instrumental variable interpretation of full information maximum likelihood (FIML) by Hausman [4] can be used to deal with the problem of simultaneous equations based on the Hamilton filter [5]. A comparison of the proposed FIML Markov-switching model with the LIML Markov-switching models [1,2,3] revealed the LIML Markov-switching models to be a special case of the proposed FIML Markov-switching model, where all but the first equation were just identified. Moreover, the proposed Markov-switching model is a general form in simultaneous equations and covers a broad class of models that could not be handled previously. Excess sensitivity of marginal propensity to consume with big shocks, such as housing bubble bursts in 2008, can be determined by applying the proposed model to Campbell and Mankiw's consumption function [6], and allowing for the possibility of structural breaks in the sensitivity of consumption growth to income growth.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.52 no.7
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• pp.315-319
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• 2003

We improved quench properties of a superconducting fault current limiter (SFCL) based on YBCO thin films by their serial and parallel combinations. The SFCL consisted of 6 switching elements fabricated of 4 inch-diameter YBCO thin films. The quench currents of the switching elements were distributed between 33.9 A and 35.6 A. Simple serial connection resulted in imbalanced power dissipation between switching elements even at the quench current difference of 0.6 A. On the other hand, $2{\times}2$ and $3{\times}2$ stack combinations produced simultaneous quenches. The $3{\times}2$ stack combination showed better simultaneous quench behavior than the $2{\times}2$ stacks. This is suggested to be because the currents between switching elements in parallel connection of the $3{\times}2$ stacks were more effectively redistributed than the $2{\times}2$ stacks.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.3
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• pp.115-119
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• 2001

This paper presents an efficient and simple method for analyzine maximum simultaneous switching noise (SSN) on ground interconnection networks in CMOS systems. For the derivation of maximum SSN expression, we use ${\alpha}$-power law MOS model and Taylor's series approximation. The accuracy of the proposed method is verified by comparing the results with those of previous researches and HSPICE simulations under the contemporary process parameters and environmental conditions. The proposed method predicts the maximum SSN values more accurately when compared to existing approaches even in most practical cases such that exist some output drivers not in transition.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.55-63
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• 1999

A new CMOS If Package design methodology is presented, analyzing the electrical characteristics of a package and its effects on the CMOS digital circuits. An analytical investigation of the package noise effects due to the simultaneous switching of the gates within a chip, i.e., simultaneous switching noise (SSN) is performed. Then not only are novel design formula to meet electrical constraints of the Package derived, but also package design methodology based on the formula is proposed. Further, in order to demonstrate the Proposed design methodology, the design results are compared with HSPICE (a general purpose circuit simulator) simulation for $0.3\mu\textrm{m}$-based CMOS circuits. According to the proposed design procedures, it is shown that the results have excellent agreements with those of HSPICE simulation.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1141-1144
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• 1998

A new design methodology for the shortchannel CMOS IC-package is presented. It is developed by representing the package inductance with an effective lumpedinductance. The worst case maximum-simultaneous-switching noise (SSN) and gate propagation delay due to the package are modeled in terms of driver geometry, the maximum number of simultaneous switching drivers, and the effective inductance. The SSN variations according to load capacitances are investigated with this model. The package design techniques based on the proposed guidelines are verified by performing HSPICE simulations with the $0.35\mu\textrm{m}$ CMOS model parameters.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.6
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• pp.44-50
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• 2002

A novel technique for minimization of simultaneous switching noise is Presented. Dual Layer Power Line (DLPL) structure i:; newly proposed for a possible silicon realization of a mutual inductor, with which an instant large current in the power line is half-divided flowing through two different, but closely coupled, layers in opposite directions. This mutual inductance between two power layers enables us to significantly reduce the switching noise. SPICE simulations show that with a mutual coupling coefficient higher than 0.8, the switching noise reduces by 63% compared to the previously reported solutions. This DLPL technique can also be applied to PCB artworks.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.41 no.6
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• pp.600-606
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• 1992

The series connection of power switching semiconductor elements is essential when a high voltage converter is made, so researches are being conducted to further develop this technology. In the series connection of power switching semiconductor elements, the main problem is that simultaneous conduction at turn-on and simultaneous blocking at turn-off together with voltage balancing are unattainable because of the difference of their switching characteristics. In this paper a novel series connection algorithm is proposed, which can implement not only the synchronization of the points of turn-on and turn-off time but the dynamic voltage balancing in spite of the difference of each switching characteristics. The proposed method is that the compensated control signal is attained from the voltage feedback signal and applied to the series-connected power transistors independently. Computer simulation and experimental results verify its validity.