• The Journal of the Korea Contents Association
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• v.21 no.4
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• pp.370-381
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• 2021

This study examines the perceptions and demands of pre-service early childhood teachers about the Demonstration of simulated instruction for 350 students in early childhood education at 3-4 years university located in Busan, Ulsan, and Gimhae. And through this, the purposes of study are to provide basic data based on the current level of pre-school teachers for instructors leading simulated instruction and to seek effective management plans for simulated instruction to improve teaching ability. As a result of the study, pre-service early childhood teachers recognized that simulated instructions were necessary in teacher training course and helped to improve teaching ability, but they did not actively agree to expand simulated instructions and were not very satisfied with the methods of instructors in demonstration of simulated instruction. They wanted to receive feedback from instructors who have practical teaching knowledge and skills based on field experience at least two times during preparation stage and evaluation stage of the simulated instructions. And they wanted to be guided specifically on principles and methods of preparing educational plans, effective interactions and questions with young children. They wanted the feedback, the most preferred form of feedback is form of participations by all class members and instructors. In addition to instructor's feedback, they required experience of simulated instruction in which infants and toddlers participate together.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.2
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• pp.103-111
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• 2019

The IoT-driven large-scaled systems consist of connected things with on-chip executable embedded software. These light-weighted embedded things have limited hardware space, especially small size of on-chip flash memory. In addition, on-chip embedded software in flash memory is not easy to update in runtime to equip with latest services in IoT-driven applications. It is becoming important to develop light-weighted IoT devices with various software in the limited on-chip flash memory. The remote instruction execution in cloud via IoT connectivity enables to provide high performance software execution with unlimited software instruction in cloud and low-power streaming of instruction execution in IoT edge devices. In this paper, we propose a Cloud-IoT asymmetric structure for providing high performance instruction execution in cloud, still low power code executable thing in light-weighted IoT edge environment using remote instruction execution. We propose a simulated approach to determine efficient partitioning of software runtime in cloud and IoT edge. We evaluated the instruction cloudification using remote instruction by determining the execution time by the proposed structure. The cloud-connected instruction set simulator is newly introduced to emulate the behavior of the processor. Experimental results of the cloud-IoT connected software execution using remote instruction showed the feasibility of cloudification of on-chip code flash memory. The simulation environment for cloud-connected code execution successfully emulates architectural operations of on-chip flash memory in cloud so that the various software services in IoT can be accelerated and performed in low-power by cloudification of remote instruction execution. The execution time of the program is reduced by 50% and the memory space is reduced by 24% when the cloud-connected code execution is used.

• ETRI Journal
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• v.30 no.1
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• pp.47-58
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• 2008

In sensor networks, analyzing power consumption before actual deployment is crucial for maximizing service lifetime. This paper proposes an instruction-level power estimator (IPEN) for sensor networks. IPEN is an accurate and fine grain power estimation tool, using an instruction-level simulator. It is independent of the operating system, so many different kinds of sensor node software can be simulated for estimation. We have developed the power model of a Micaz-compatible mote. The power consumption of the ATmega128L microcontroller is modeled with the base energy cost and the instruction overheads. The CC2420 communication component and other peripherals are modeled according to their operation states. The energy consumption estimation module profiles peripheral accesses and function calls while an application is running. IPEN has shown excellent power estimation accuracy, with less than 5% estimation error compared to real sensor network implementation. With IPEN's high precision instruction-level energy prediction, users can accurately estimate a sensor network's energy consumption and achieve fine-grained optimization of their software.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.226-229
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• 2000

In this paper, we describe implementation of 32-Bit RISC Core for portable communication/information equipment, such as cellular telephones and personal digital assistants, notebook, etc. The RISC core implements the ARM$\^$R/V4 instruction set on the basis of low power techniques in architecture level and logic level. It operates with 5-stage pipeline, and has harvard architecture to increase execution speed. The processor is modeled and simulated in RTL level using VHDL. Behavioral Cache and MMU are added to the VHDL model for instruction level verification of the processor. The core is implemented using Mentor P'||'&'||'R tools with IDEC C-631 Cell library of 0.6$\mu\textrm{m}$ CMOS 1-poly 3-metal CMOS technology.

• International Journal of Contents
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• v.5 no.2
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• pp.53-58
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• 2009

This paper presents a novel approach in the design of a CAM for an asynchronous cache. The architecture of cache mainly consists of four units: control logics, content addressable memory, completion signal logic units and instruction memory. The pseudo-DCVSL is useful to make a completion signal which is a reference for handshake control. The proposed CAM is a very simple extension of the basic circuitry that makes a completion signal based on DI model. The cache has 2.75KB CAM for 8KB instruction memory. We designed and simulated the proposed asynchronous cache including CAM. The results show that the cache hit ratio is up to 95% based on pseudo-LRU replacement policy.

• Journal of the Korea Society of Computer and Information
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• v.5 no.3
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• pp.16-28
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• 2000

In this paper, we implemented by describing a pipeline processor using a HDL in functional level, simulated and verified it's operation. When simulating a implemented processor. We first specify assembly instruction that is Performed in the processor. entered by programming using the instruction sets at the experimental framework. Thus, the procedure that is presented in this paper can easily identify and verify the purpose for implementation and operation of a system by using test vector. Also, it was possible that exactly simulate a system. The method was comfortable that document a system operation to implement.

• Journal of the Korean association of regional geographers
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• v.17 no.4
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• pp.459-476
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• 2011

This research aims to figure out the impact of different reflective thinking methods on pre-service geography teachers' teaching knowledge. Four pre-service teachers in the same level were selected through the first simulated instruction, Then, different reflective methods were given them to carry out the reflection. Afterwards, they carried out their second simulated instruction. The change of average score of pre-service teachers was analyzed through the peer reviews and Paired samples T-test. The results are as follows. First, when the first peer review score were compared with second peer review, average score of all pre-service teachers improved. But, pre-service teachers who got cooperative reflection with a specialist had the widest variation in the increase level of average score comparing to those without reflection or reflective journal writing. Second, reflective journal writing through self-reflection led to their reflective thinking, but it did not induce them to reflective practice. Finally, pre-service teacher who got cooperative reflection with experienced teachers got the significant improvement in PCK through the T-test. In particular, it had significant statistical value in instruction section and understanding of students section. It demonstrates that the contextual section could be improved by self-reflection or repetitive class practices, while instruction section and understanding of students section needed consulting by assistants.

• Journal of The Korean Association For Science Education
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• v.32 no.7
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• pp.1157-1168
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• 2012

This study examined the effect of simulated instruction activities based on a constructivist teaching approach on epistemological belief, science teaching efficacy belief, and teaching motivation. The RTOP (Reformed Teaching Observation Protocol) played a role to guide preservice biology teachers to obtain insights on current reformed teaching and to further practice teaching based on constructivism. The results indicated that preservice teachers changed their epistemological beliefs toward more sophisticated views, especially for 'simple knowledge'. They also improved their science teaching efficacy beliefs, both personal science teaching efficacy belief (PSTEB) and science teaching outcome expectancy (STOE). In addition, these perservice teachers decreased their scores of extrinsic teaching motivation. The Pearson correlation represented the negative relationship between personal science teaching efficacy belief (PSTEB) and extrinsic teaching motivation. After intervention, the preservice teachers mentioned inquiry, active participation and discussion as ideal science teaching methods and qualifications for science teachers.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.3
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• pp.142-148
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• 2008

Though a deblocking filter of H.264/AVC provides enhanced image quality by removing blocking artifact on block boundary, the complex filtering operation on this process is a dominant factor of the whole decoding time. In this paper, we designed an ASIP to accelerate deblocking filter operation with the proposed instruction set. We designed a processor based on a MIPS structure with LISA, simulated a deblocking later model, and compared the execution time on the proposed instruction set. In addition, we generated HDL model of the processor through CoWare's Processor Designer and synthesized with TSMC 0.25um CMOS cell library by Synopsys Design Compiler. As the result of the synthesis, the area and delay time increased 7.5% and 3.2%, respectively. However, due to the proposed instruction set, total execution performance is improved by 18.18% on average.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.66-76
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• 1998

In this paper, we implement a buffer capable of handling short loops references to statistically lower the miss rate of variable-length instructions stored in the instruction buffer. MAU(Mark Appending Unit) takes the instructions as they are fetched from external memory, performs some initial decode operations and stores the results of the decode in the buffer for reducing multiple decodes when instructions are executed repeatedly such as in a loop. It includes a decision block of whether hit or not for effectively processing branch instructions Each module of the proposed architecture of processing variable-length instruction is described in VHDL structurally and behaviorally and whether it is working well or not is checked on V-System simulator of Model Technology Inc. We synthesized and simulated the architecture using an ASIC Synthesizer tool with 0.6$\mu\textrm{m}$ 5-Volt CMOS COMPASS library. Operation speed is up to 140MHz. The architecture includes about 17,000 gates.