• Title/Summary/Keyword: simple processing

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Microbiological and Physicochemical Hazard Analysis in Processing Process of Simple-Processed Shellfish Products (단순가공 패류의 수산물의 가공 공정 중 미생물학적 및 이화학적 위해요소 분석)

  • Kwon, Kion;Ryu, Dae-Gyu;Jeong, Min-Chul;Kang, Eun-Hye;Shin, Il-Shik;Kim, Young-Mog
    • Korean Journal of Fisheries and Aquatic Sciences
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    • v.50 no.4
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    • pp.352-358
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    • 2017
  • The object of this study is to assess physicochemical and microbiological hazards involved during the processing of shellfish products such as oysters, clam, and mussels. Samples including raw materials, intermediates, and final products in the processing process were collected from seven simple-processed shellfish facilities. In the samples obtained from the facilities, viable cell count and coliform group were detected less than that of the Korean Government guidelines. In addition, the high-risk bacterial pathogens such as Escherichia coli O157:H7, Salmonella sp., and Listeria monocytogenes were not identified in raw materials and final products. However, the low-risk pathogens, Staphylococcus aureus and Vibrio parahaemolyticus, were detected in some final products. The level of heavy metal content in the final products tested in this study meets the recommendations by the Korean Government standard guidelines. No foreign materials in the final products were also observed. Considering these results, it was concluded that no significant food hazards exists in the processing process of simple-processed shellfish products. However, it is essential to improve the food safety control in the shellfish processing facilities since S. aureus, a personal sanitary indicative bacterium, was continuously detected over seven simple-processed shellfish facilities.

Design and Evaluation of an Adaptive Reservation-based Batching Polity for Popular Videos (인기 있는 비디오를 위한 적응적 예약기반 일괄처리 정책의 설계 및 평가)

  • Lee, Gyeong-Suk;Bae, In-Han
    • The Transactions of the Korea Information Processing Society
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    • v.6 no.10
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    • pp.2790-2796
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    • 1999
  • In video-on-demand systems, the I.O bandwidth of video servers is the critical resource which contributes to increase in latency. Several approaches: bridging, piggybacking are used to reduce the I/O demand on the video server through sharing. Batching delays the requests for the different videos for a batching window so that more requests for the same video arriving during the current batching window may be served using the same stream. In this paper, we propose an adaptive reservation-based batching policy which dynamically reserves video server capacity for popoular videos according to video server loads. The performance of the proposed policy is evaluated through a simulation, and is compared with simple batching and static reservation-based batching policies. As the result, we know that the adaptive reservation-based batching policy more improves service ratio and average waiting time than simple batching and simple reservation-based batching policy more improves service ratio and average waiting time than simple batching and simple reservation-based batching polices.

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Traffic flow measurement system using image processing

  • Hara, Takaaki;Akizuki, Kageo;Kawamura, Mamoru
    • 제어로봇시스템학회:학술대회논문집
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    • 1996.10a
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    • pp.426-439
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    • 1996
  • In this paper, we propose a simple algorithm to calculate the numbers of the passing cars by using an image processing sensor for the digital black and white images with 256 tone level. Shadow is one of the most troublesome factor in image processing. By differencing the tone level, we cannot discriminate between the body of the car and its shadow. In our proposed algorithm, the area of the shadow is excluded by recognizing the position of each traffic lane. For real-time operation and simple calculation, two lines of the tone level are extracted and the existences of cars are recognized. In the experimental application on a high-way, the recognition rate of the real-time operation is more than 94%.

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A Special Case of Three Machine Flow Shop Scheduling

  • Yang, Jaehwan
    • Industrial Engineering and Management Systems
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    • v.15 no.1
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    • pp.32-40
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    • 2016
  • This paper considers a special case of a three machine flow shop scheduling problem in which operation processing time of each job is ordered such that machine 1 has the longest processing time, whereas machine 3, the shortest processing time. The objective of the problem is the minimization of the total completion time. Although the problem is simple, its complexity is yet to be established to our best knowledge. This paper first introduces the problem and presents some optimal properties of the problem. Then, it establishes several special cases in which a polynomial-time optimal solution procedure can be found. In addition, the paper proves that the recognition version of the problem is at least binary NP-complete. The complexity of the problem has been open despite its simple structure and this paper finally establishes its complexity. Finally, a simple and intuitive heuristic is developed and the tight worst case bound on relative error of 6/5 is established.

Unrelated Parallel Processing Problems with Weighted Jobs and Setup Times in Single Stage (가중치와 준비시간을 포함한 병렬처리의 일정계획에 관한연구)

  • Goo, Jei-Hyun;Jung, Jong-Yun
    • Journal of Korean Institute of Industrial Engineers
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    • v.19 no.4
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    • pp.125-135
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    • 1993
  • An Unrelated Parallel Processing with Weighted jobs and Setup times scheduling prolem is studied. We consider a parallel processing in which a group of processors(machines) perform a single operation on jobs of a number of different job types. The processing time of each job depends on both the job and the machine, and each job has a weight. In addition each machine requires significant setup time between processing jobs of different job types. The performance measure is to minimize total weighted flow time in order to meet the job importance and to minimize in-process inventory. We present a 0-1 Mixed Integer Programming model as an optimizing algorithm. We also present a simple heuristic algorithm. Computational results for the optimal and the heuristic algorithm are reported and the results show that the simple heuristic is quite effective and efficient.

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Implementation of simple statistical pattern recognition methods for harmful gases classification using gas sensor array fabricated by MEMS technology (MEMS 기술로 제작된 가스 센서 어레이를 이용한 유해가스 분류를 위한 간단한 통계적 패턴인식방법의 구현)

  • Byun, Hyung-Gi;Shin, Jeong-Suk;Lee, Ho-Jun;Lee, Won-Bae
    • Journal of Sensor Science and Technology
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    • v.17 no.6
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    • pp.406-413
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    • 2008
  • We have been implemented simple statistical pattern recognition methods for harmful gases classification using gas sensors array fabricated by MEMS (Micro Electro Mechanical System) technology. The performance of pattern recognition method as a gas classifier is highly dependent on the choice of pre-processing techniques for sensor and sensors array signals and optimal classification algorithms among the various classification techniques. We carried out pre-processing for each sensor's signal as well as sensors array signals to extract features for each gas. We adapted simple statistical pattern recognition algorithms, which were PCA (Principal Component Analysis) for visualization of patterns clustering and MLR (Multi-Linear Regression) for real-time system implementation, to classify harmful gases. Experimental results of adapted pattern recognition methods with pre-processing techniques have been shown good clustering performance and expected easy implementation for real-time sensing system.

Blocking Artifacts Reduction with Constrained Random Modification of Block Boundary Pixels

  • Lee, Insuh;Yongsul Joe;Byeungwoo Jeon
    • Proceedings of the IEEK Conference
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    • 2000.07a
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    • pp.35-38
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    • 2000
  • Low bit rate image/video coding is essential for many visual communication applications. When bit rates become low, most compression algorithms yield visually blocking artifacts that highly degrade the perceptual quality, and post-processing approaches provide one attractive solution. In this paper, we provide simple and very efficient blocking artifacts reduction method using constrained random value addition. Our method is simple enough to be used for real-time post-processing of video.

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FFT Array Processor System with Easily Adjustable Computation speed and Hardware Complexity (계산속도와 하드웨어 양이 조절 용이한 FFT Array Processor 시스템)

  • Jae Hee Yoo
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.30A no.3
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    • pp.114-129
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    • 1993
  • A FFT array processor algorithm and architecture which anc use a minumum required number of simple, duplicate multiplier-adder processing elements according to various computation speed, will be presented. It is based on the p fold symmetry in the radix p constant geometry FFT butterfly stage with shuffled inputs and normally ordered outputs. Also, a methodology to implement a high performance high radix FFT with VLSI by constructing a high radix processing element with the duplications of a simple lower radix processing element will be discussed. Various performances and the trade-off between computation speed and hardware complexity will be evaluated and compared. Bases on the presented architecture, a radix 2, 8 point FFT processing element chip has been designed and it structure and the results will be discusses.

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Distributed Image Preprocessing using Object Activation (객체 활성화를 이용한 분산 영상처리)

  • Heo, Jin-Kyoung
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.11 no.1
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    • pp.87-92
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    • 2011
  • Server overload is directly proportional to requested image data size in a image processing. If request data are increase then system is overloaded in a image processing system. For the reduce of server bottle neck, we will be able to consider a distributed processing. Simple distributed processing system can solve server bottleneck and system overload but high cost system requirements. In this paper, Proposes a new distributed image processing system. Object activation technology are being grafted on to simple distributed processing system. It can optimize the user of system resources and can reuse idle system resources in network.

Design of Floating-point Processing Unit for Multi-chip Superscalar Microprocessor (다중 칩 수퍼스칼라 마이크로프로세서용 부동소수점 연산기의 설계)

  • 이영상;강준우
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.1153-1156
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    • 1998
  • We describe a design of a simple but efficient floatingpoint processing architecture expoiting concurrent execution of scalar instructions for high performance in general-purpose microprocessors. This architecture employs 3 stage pipeline asyncronously working with integer processing unit to regulate instruction flows between two arithmetic units.

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