• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.283-284
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• 2012

In this work, a special technique called dielectric filling was carried out in order to reduce sub-threshold leakage current inside double-gated n-channel MOSFET. This calibration was done by using SILVACO Atlas(TCAD), and the result showed quite a good performance compared to the conventional double-gate MOSFET.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.2
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• pp.48-54
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• 1999

We designed the optimal device parameters of the retrograde well and the gettering layer(buried layer) using the high energy ion implantation for the next generation of CMOS struoture and proposed two models and simulated these models with Athena and Atlas, Silvaco Co. We obtained trigger currents which is more than 600 ${\mu}A/{\mu}m$ when the structure has been combined the gettering layer and the retrograde well. And the second model(twin retrograde well) was obtained that holdingcurrents were over 2500${\mu}A/{\mu}m$. As results, the more heavier dose, the more improved the latch-up immunity. The n'-p' spacing was fixed a 2${\mu}m$ in both models.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.6
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• pp.890-898
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• 2001

4H-SiC(silicon carbide) MESFET large signal model was studied using modified Materka-Kacprzak large signal MESFET model. 4H-SiC MESFET device simulation have been conducted by Silvaco\`s 2D device simulator, ATLAS. The result is modeled using modified Materka large signal model. simulation and modeling results are -8 V pinch off voltage, under V$\_$GS/=0 V, V$\_$DS/=25 V conditions, I$\_$DSS/=270 mA/mm, G$\_$m/=52.8 ms/mm were obtained. Through the power simulation 2 GHz, at the bias of V$\_$GS/-4 V md V$\_$DS/=25 V, 10 dB Gain, 34 dBm (1dB compression point)output porter, 7.6 W/mm power density, 37% PAE(power added efficiency) were obtained.7.6 W/mm power density, 37% PAE(power added efficiency) were obtained.d.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.109-114
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• 2013

Power MOSFET (metal-oxide semiconductor field-effect transistor) are widely used in power electronics applications, such as BLDC (Brushless Direct Current) motor and power module, etc. For the conventional power MOSFET device structure, there exists a tradeoff relationship between specific on-state resistance and breakdown voltage. In order to overcome the tradeoff relationship, a non-uniform super-junction (SJ) trench MOSFET (TMOSFET) structure for an optimal design is proposed in this paper. It is required that the specific on-resistance of non-uniform SJ TMOSFET is less than that of uniform SJ TMOSFET under the same breakdown voltage. The idea with a linearly graded doping profile is proposed to achieve a much better electric field distribution in the drift region. The structure modelling of a unit cell, the characteristic analyses for doping density, and potential distribution are simulated by using of the SILVACO TCAD 2D device simulator, Atlas. As a result, the non-uniform SJ TMOSFET shows the better performance than the uniform SJ TMOSFET in the specific on-resistance at the class of 100V.

• Journal of IKEEE
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• v.17 no.4
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• pp.428-433
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• 2013

In this study, an 4H-SiC Trench MOS Barrier Schottky (TMBS) rectifier which utilizes the trapezoid mesa structure and the upper half of the trench sidewall is proposed to improve the forward voltage drop and reverse blocking voltage concurrently. The proposed 4H-SiC TMBS rectifier reduces the forward voltage drop by 12% compared to the conventional 4H-SiC TMBS rectifier with the tilted sidewall and improves the reverse blocking voltage by 11% with adjusting the length of the upper sidewall. The Silvaco T-CAD was used to analyze the electrical characteristics.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.229-232
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• 2001

4H-SIC(silicon carbide) MESFET large signal model was studied using modified Materka-Kacprzak large signal MESFET model. 4H-SiC MESFET device simulation have been conducted by Silvaco's 2D device simulator, ATLAS. The result is modeled using modified Materka large signal model. simulation and modeling results are -8V pinch off voltage, under $V_{GS=0V}$, $V_{DS=25V}$ conditions, $I_{DSS=270㎃}$mm, $G_{m=45㎳}$mm were obtained. Through the power simulation 2GHz, at the bias of $V_{GS=-4V}$ and $V_{DS=25V}$, 10dB Gain, 34dBm(1dB compression point)output power, 7.6W/mm power density, 37% PAE(power added efficiency) were obtained.d.d.d.

• 한국신재생에너지학회:학술대회논문집
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• 2011.11a
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• pp.57.2-57.2
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• 2011

Dye-sensitized solar cells (DSSC) have recently been developed as a cost-effective photovoltaic system due to their low-cost materials and facile processing. The production of DSSC involves chemical and thermal processes but no vacuum is involved. Therefore, DSSC can be fabricated without using expensive equipment. The use of dyes and nanocrystalline $TiO_2$ is one of the most promising approaches to realize both high performance and low cost. The efficiency of the DSSC changes consequently in the particle size, morphology, crystallization and surface state of the $TiO_2$. Nanocrystalline $TiO_2$ materials have been widely used as a photo catalyst and an electron collector in DSSC. Front electrode in DSSC are required to have an extremely high porosity and surface area such that the dyes can be sufficiently adsorbed and be electronically interconnected, resulting in the efficient generation of photocurrent within cells. In this study, DSSC were fabricated by an screen printing for the $TiO_2$ thin film. $TiO_2$ nanoparticles characterized by X-ray diffractometer (XRD) and scanning electron microscope (SEM) and scanning auger microscopy (SAM) and zeta potential and electrochemical impedance spectroscopy(EIS).In addition, DSSC module was modeled and simulated using the SILVACO TCAD software program. Improve the efficiency of DSSC, the effect of $TiO_2$ thin film thickness and $TiO_2$ nanoparticle size was investigated by SILVACO TCAD software program.

• Journal of IKEEE
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• v.16 no.4
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• pp.283-289
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• 2012

In this paper, We proposed Separate Gate Technique(SGT) to improve the switching characteristics of Trench power MOSFET. Low gate-to-drain 전하 (Miller 전하 : Qgd) has to be achieved to improve the switching characteristics of Trench power MOSFET. A thin poly-silicon deposition is processed to form side wall which is used as gate and thus, it has thinner gate compared to the gate of conventional Trench MOSFET. The reduction of the overlapped area between the gate and the drain decreases the overlapped charge, and the performance of the proposed device is compared to the conventional Trench MOSFET using Silvaco T-CAD. Ciss(input capacitance : Cgs+Cgd), Coss(output capacitance : Cgd+Cds) and Crss(reverse recovery capacitance : Cgd) are reduced to 14.3%, 23% and 30% respectively. To confirm the reduction effect of capacitance, the characteristics of inverter circuit is comprised. Consequently, the reverse recovery time is reduced by 28%. The proposed device can be fabricated with convetional processes without any electrical property degradation compare to conventional device.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1671-1673
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• 1999

일반적으로 SOI 소자에 대한 연구는 film 두께. 채널길이 그리고 doping 농도에 따라 폭넓게 연구되어 왔다. 제안한 소스/드레인 비대칭 SOI 소자는 일반적인 LDD SOI 소자와 비교하여 항복전압은 거의 비슷한 반면. 전류 구동능력은 훨씬향상된 소자를 구현 시킬수 있었다. 비대칭 SOI 소자를 설계하기 위하여 최적화된 공정조건을 모의 실험용 TCAD Simulator (SILVACO)를 이용하여 검증하였다. 검증된 공정 변수를 이용하여 모의 실험을 해보았더니 항복전압과 전류 구동능력에서 좋은 특성을 나타내었다.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.557-560
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• 2004

In this study, we design the one-chip PWM IC for SMPS (Switching Mode Power Supply) application. We determine the IC spec. and simulated each block of PWM IC (Reference, Error amp., Comparator, Oscillator) with Smart Spice (SILVACO Circuit Simulation Tool). Reference circuits generate constant voltage(5V) in the various of power supply and temperature condition. Error amp. is designed with large DC gain (${\simeq}65dB$), unity frequency (${\simeq}190kHz$) and large PM($75^{\circ}$).Saw tooth generators operate with 20K oscillation frequency (external resistor, capacitor).