• 대한전자공학회논문지SD
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• 제44권12호
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• pp.31-36
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• 2007

본 논문은 100 nm BSIMSOI 3.2 기술을 사용한 부분 공핍형 SOI (Partially-Depleted SOI: PD-SOI) 회로들의 정확한 타이밍 분석을 위한 새로운 통계적 특징화 방법과 추정 방법을 제안한다. 제안된 타이밍 추정 방법은 Matlab, Hspice, 그리고 C 언어로 구현되고, ISCAS 85 벤치마크 회로들을 사용해서 검증된다. 실험 편과는 Monte Carlo 시뮬레이션과 비교해 5 % 내의 에러를 보여준다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.918-921
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• 1999

The breakdown voltage in fully depleted SOI N-MOSFET’s have been studied over a wide range of film thicknesses, channel doping, and channel lengths. An asynmmetric Source/Drain SOI technology is proposed, which having the advantages of Normal LDD SOI(Silicon-On-Insulator) for breakdown voltage and gives a high drivability of LDD SOI without sacrificings hot carrier immunity The two-dimensional simulations have been used to investigate the breakdown behavior in these device. It is found that the breakdown voltage(BVds) is almost same with high current drivability as that in Normal LDD SOI device structure.

• 한국결정성장학회지
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• 제5권2호
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• pp.100-108
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• 1995

SOI구조를 얻기 위한 방법의 한가지인 ZMR공정에 있어서 열전달은 계면의 위치와 모양을 결정하는 중요한 역할을 한다. 본 연구에서는 SOI구조를 얻기 위한 ZMR공정중의 열전달 공정을 모사할 수 있는 의사정상상태 2차원 ZMR모델을 수립하였다. 본 모델은 복사, 전도 그리고 대류 열전달을 포함하며, 고/액 계면의 위치를 결정한다. 모델로부터 구한 수치해는 실리콘 기판의 용융부에서의 유동장, 전체 SOR구조에서의 온도장 그리고 실리콘 박막과 기판에서의 고/액 계면의 위치를 포함한다. 여러 공정 변수들의 변화에 따른 온도장과 계면의 형상과 폭의 변화를 알아보았다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 학술대회지
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• pp.482-485
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• 2004

We fabricated a hybrid bulk/fully depleted silicon on insulator (FDSOI) complementary metal oxide semiconductor (CMOS) active pixel image sensor. The active pixel is comprised of reset and source follower transistors on the SOI seed wafer, while the pinned photodiode and readout gate and floating diffusion are fabricated on the SOI handle wafer after the removal of the buried oxide. The source of dark current is eliminated by hybrid bulk/FDSOI pixel structure between localized oxidation of silicon (LOCOS) and photodiode(PD). By using the low noise hybrid pixel structure, dark currents qm be suppressed significantly. The pinned photodiode can also be optimized for quantum efficiency and reduce the noise of dark current. The spectral response of the pinned photodiode on the SOI handle wafer is very flat between 400 nm and 700 nm and the dark current that is higher than desired is about 10 nA/cm2 at a $V_{DD}$ of 2 V.

• 한국진공학회지
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• 제10권3호
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• pp.361-367
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• 2001

CMP(Chemical Mechanical Polishing)는 반도체 소자 제조공정 중 다층 배선구조의 평탄 경면화에 널리 이용되고 있다. 차세대 웨이퍼로 각광받는 SOI(Silicon On Insulator) 웨이퍼 제조공정 중 웨이퍼 표면 미소 거칠기를 개선하기 위해서 본 논문에서는 여러 가지 가공변수(슬러리와 연마패드)에 따른 CMP 연마능률과 표면 미소 거칠기 변화에 대해 연구하였다. 결과적으로 연마능률은 슬러리의 입자 크기가 증가할수록 이에 따라 증가하였으며, 미소 거칠기는 슬러리의 연마입자보다는 연마패드에 영향이 더욱 지배적이다. AFM(Atomic Force Microscope)에 의한 평가에서 표면 미소 거칠기가 27 $\AA$ Rms에서 0.64 $\AA$ Rms로 개선됨을 확인할 수 있었다.

• Transactions on Electrical and Electronic Materials
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• 제2권4호
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• pp.30-32
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• 2001

In this paper, a new silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) is proposed to improve the latch-up performance without current path underneath the n$^{+}$ cathode region. The improvement of latch-up performance is verified using the two- dimensional simulator MEDICI and the simulation results on the latch-up current density are 4468 A/cm2 for the proposed LIGBT and 1343 A/$\textrm{cm}^2$ for the conventional LIGBT. The proposed SOI LIGBT exhibits 3 times larger latch-up capability than the conventional SOI LIGBT.T.

• Transactions on Electrical and Electronic Materials
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• 제1권1호
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• pp.6-11
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• 2000

The hydrogen plasma treatment of silicon wafers in the reactive ion-etching mode was studied for the application to silicon-on-insulator wafers which were prepared using the wafer bonding technique. The chemical reactions of hydrogen plasma with surface were used for both surface activation and removal of surface contaminants. As a result of exposure of silicon wafers to the plasma, an active oxide layer was found on the surface. This layer was rendered hydrophilic. The surface roughness and morphology were examined as functions of the plasma exposing time and power. In addition, the surface became smoother with the shorter plasma exposing time and power. The value of initial surface energy estimated by the crack propagation method was 506 mJ/㎡, which was up to about three times higher as compared to the case of conventional direct using the wet RCA cleaning method.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 춘계학술대회 논문집 센서 박막재료 반도체 세라믹
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• pp.170-173
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• 2003

In this paper, we proposed a new bulk LDMOS structure which can be used for RF application, and its fabrication steps were introduced. The simulated devices consist of three types: Bulk device, SLB(SOI Like Bulk), and SOI device. As a result of process and device simulation, we showed electrical characteristics, such as threshold voltage, subthreshold slope, DIBL(Drain Induced Barrier Lowering), off-state current, and breakdown voltage. In this simulation study, the lattice temperature model was adopted to see the device characteristics with lattice temperature during the operation. SLB device structure showed the best breakdown characteristics among the other structures. The breakdown voltage of SLB structure is about 9V, that of bulk is 7V, and that of SOI is 8V.

• 한국재료학회지
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• 제14권6호
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• pp.413-419
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• 2004

Recently, Silicon On Insulator (SOI) devices emerged to achieve better device characteristics such as higher operation speed, lower power consumption and latch-up immunity. Nevertheless, there are many detrimental defects in SOI wafers such as hydrofluoric-acid (HF)-defects, pinhole, islands, threading dislocations (TD), pyramid stacking faults (PSF), and surface roughness originating from quality of buried oxide film layer. Although the number of defects in SOI wafers has been greatly reduced over the past decade, the turn over of high-speed microprocessors using SOI wafers has been delayed because of unknown defects in SOI wafers. A new characterization method is proposed to investigate the crystalline quality, the buried oxide integrity and some electrical parameters of bonded SOI wafers. In this study, major surface defects in bonded SOI are reviewed using HF dipping, Secco etching, Cu-decoration followed by focused ion beam (FIB) and transmission electron microscope (TEM).

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권4호
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• pp.223-226
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• 2003

The EKV model, a continuous model for the MOS transistor, has been adapted to both partially depleted SOI MOSFETs with grounded body (GBSOI) and dynamic threshold MOS (DTMOS) transistors. Adaptation is straightforward and helps to understand the physics of the DTMOS. Excellent agreement is found between the model and the measured characteristics of GBSOI and DTMOS devices