• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2006.10a
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• pp.10-13
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• 2006

This paper describes on the fabrication and characteristics of a 3C-SiC (Silicon Carbide) micro pressure sensor for harsh environment applications. The implemented micro pressure sensor used 3C-SiC thin-films heteroepitaxially grown on SOI (Si-on-insulator) structures. This sensor takes advantages of the good mechanical properties of Si as diaphragms fabricated by D-RIE technology and temperature properties of 3C-SiC piezoresistors. The fabricated pressure sensors were tasted at temperature up to $250^{\circ}C$ and indicated a sensitivity of 0.46 mV/V*bar at room temperature and 0.28 mV/V*bar at $250^{\circ}C$. The fabricated 3C-Sic/SOI pressure sensor presents a high-sensitivity and excel lent temperature stability.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.274-274
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• 2008

This paper describes on the fabrication and characteristics of a 3C-SiC (Silicon Carbide) micro pressure sensor for harsh environment applications. The implemented micro pressure sensor used 3C-SiC thin-films heteroepitaxially grown on SOI (Si-on-insulator) structures. This sensor takes advantages of the good mechanical properties of Si as diaphragms fabricated by D-RIE technology and temperature properties of 3C-SiC piezoresistors. The fabricated pressure sensors were tasted at temperature up to $250^{\circ}C$ and indicated a sensitivity of 0.46 mV/V*bar at room temperature and 0.28 mV/V*bar at $250^{\circ}C$. The fabricated 3C-SiC/SOI pressure sensor presents a high-sensitivity and excellent temperature stability.

• ETRI Journal
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• v.30 no.4
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• pp.516-525
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• 2008

This paper proposes a compact, energy-efficient, and smart gas sensor platform technology for ubiquitous sensor network (USN) applications. The compact design of the platform is realized by employing silicon-on-insulator (SOI) technology. The sensing element is fully integrated with SOI CMOS circuits for signal processing and communication. Also, the micro-hotplate operates at high temperatures with extremely low power consumption, which is important for USN applications. ZnO nanowires are synthesized onto the micro-hotplate by a simple hydrothermal process and are patterned by a lift-off to form the gas sensor. The sensor was operated at $200^{\circ}C$ and showed a good response to 100 ppb $NO_2$ gas.

• ETRI Journal
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• v.35 no.4
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• pp.638-643
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• 2013

This paper presents a 5-bit digital step attenuator (DSA) using a commercial 0.18-${\mu}m$ silicon-on-insulator (SOI) process for the wideband phased array antenna. Both low insertion loss and low root mean square (RMS) phase error and amplitude error are achieved employing two attenuation topologies of the switched path attenuator and the switched T-type attenuator. The attenuation coverage of 31 dB with a least significant bit of 1 dB is achieved at DC to 20 GHz. The RMS phase error and amplitude error are less than $2.5^{\circ}$ and less than 0.5 dB, respectively. The measured insertion loss of the reference state is less than 5.5 dB at 10 GHz. The input return loss and output return loss are each less than 12 dB at DC to 20 GHz. The current consumption is nearly zero with a voltage supply of 1.8 V. The chip size is $0.93mm{\times}0.68mm$, including pads. To the best of the authors' knowledge, this is the first demonstration of a low phase error DC-to-20-GHz SOI DSA.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.110-111
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• 2006

이중 에피층을 가지는 SOI (Silicon-On-Insulator) RESURF(REduced SURface Field) LIGBT(Lateral Insulated Gate Bipolar Transistor) 소자의 에피층 두께에 따른 항복전압 특성을 분석하였다. 이중 에 피층 구조를 가지는 SOI RESURF LIGBT 소자는 전하보상효과를 얻기 위해 기존 LIGBT 소자의 n 에피로 된 영역을 n/p 에피층의 이중 구조로 변경한 소자로 n/p 에피층 영역내의 전하간 상호작용에 의해 에피 영역 전체가 공핍됨으로써 높은 에피 영역농도에서도 높은 항복전압을 얻을 수 있는 소자이다. 본 논문에서는 LIGBT 에피층의 전체 두께와 농도를 고정한 상태에서 n/p 에피층의 두께가 변하는 경우에 항복전압 특성의 변화에 대해 simulation을 통해 분석하였다.

• Journal of the Optical Society of Korea
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• v.20 no.2
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• pp.291-299
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• 2016

We have investigated the ultimate limits of nonuniform grating couplers (NGCs) for optimized fiber coupling to silicon waveguides, compared to uniform grating couplers (UGCs). Simple grating coupler schemes, which can be fabricated in etching steps of the conventional complementary metal-oxide semiconductor (CMOS) process on silicon-on-insulator (SOI) wafers without forming any additional overlay structure, have been simulated numerically and demonstrated experimentally. Optimum values of the grating period, fill factor, and groove number for ultimate coupling efficiency of the NGCs are determined from finite-difference time-domain (FDTD) simulation, and confirmed with experimentally demonstrated devices by comparison to those for the UGCs. Our simulated results indicate that maximum coupling efficiency of NGCs is possible when the minimum pattern size is below 50 nm, but the experimental value for the maximum coupling efficiency is limited by the attainable fabrication tolerance in a practical device process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.36-36
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• 2009

In this work, we describe a method to fabricate the Pt-silicided SB-MOSFETs with a n-type Silicon-On-Insulator (SOI) substrate as an active layer and demonstrate their electrical and structural properties. The fabricated SB-MOSFETs have novel structure and metal gate without sidewall. The gate oxide with a thickness of 7 nm was deposited by sputtering. Also, this fabrication processes were carried out below $500^{\circ}C$. As a result, Subthreshold swing value and on/off ratio of Fabricated SB MOSFETs was 70 [mV/dec] and $10^8$.

• Vacuum Magazine
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• v.3 no.1
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• pp.16-21
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• 2016

FinFETs are able to be scaled down to 22 nm and beyond while suppressing effectively short channel effect, and have superior performance compared to 2-dimensional (2-D) MOSFETs. Bulk FinFETs are built on bulk Si wafers which have less defect density and lower cost than SOI(Silicon-On-Insulator) wafers. In contrast to SOI FinFETs, bulk FinFETs have no floating body effect and better heat transfer rate to the substrate while keeping nearly the same scalability. The bulk FinFET has been developed at 14 nm technology node, and applied in mass production of AP and CPU since 2015. In the development of the bulk FinFETs at 10 nm and beyond, self-heating effects (SHE) is becoming important. Accurate control of device geometry and threshold voltage between devices is also important. The random telegraph noise (RTN) would be problematic in scaled FinFET which has narrow fin width and small fin height.

• Transactions on Electrical and Electronic Materials
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• v.18 no.1
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• pp.25-29
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• 2017

This paper presents a unique pressure sensor design for environmental applications. The design uses a new geometry for a multi bossed beam-membrane structure with a SOI (silicon-on-insulator) substrate and a mechanical transducer. The Intellisuite MEMS CAD design tool was used to build and analyze the structure with FEM (finite element modeling). The working principle of the multi bossed beam structure is explained. FEM calculations show that a sensing diaphragm with Mises stress can provide superior linear response compared to a stress-free diaphragm. These simulation results are validated by comparing the estimated deflection response. The results show that, the sensitivity is enhanced by using both the novel geometry and the SOI substrate.

• Journal of Magnetics
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• v.18 no.2
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• pp.163-167
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• 2013

We fabricated prototype cantilevers for mechanically detected high-frequency ESR measurement. Cantilevers are fabricated from silicon-on-insulator (SOI) wafers using standard MEMS techniques such as lithography, wet etching, and plasma etching. Using commercial SOI wafers, fabrication cost and the number of processes can be substantially reduced. In this study, three types of cantilevers, designed for capacitive and optical detection, are shown. Capacitive type with lateral dimensions of $3.5{\times}1.6mm^2$ is aimed for low spin concentration sample. On the other hand, optical detection type with lateral dimensions of $50{\times}200{\mu}m^2$ is developed for high-sensitive detection of tiny samples such as newly synthesized microcrystals.