• JSTS:Journal of Semiconductor Technology and Science
• /
• v.3 no.4
• /
• pp.217-222
• /
• 2003

A new two-dimensional analytical model for the potential distribution and drain-induced barrier lowering (DIBL) effect of fully depleted short-channel Silicon-on-insulator (SOI)-MESFET's has been presented in this paper. The two dimensional potential distribution functions in the active layer of the device is approximated as a simple parabolic function and the two-dimensional Poisson's equation has been solved with suitable boundary conditions to obtain the bottom potential at the Si/oxide layer interface. It is observed that for the SOI-MESFET's, as the gate-length is decreased below a certain limit, the bottom potential is increased and thus the channel barrier between the drain and source is reduced. The similar effect may also be observed by increasing the drain-source voltage if the device is operated in the near threshold or sub-threshold region. This is an electrostatic effect known as the drain-induced barrier lowering (DIBL) in the short-gate SOI-MESFET's. The model has been verified by comparing the results with that of the simulated one obtained by solving the 2-D Poisson's equation numerically by using the pde toolbox of the widely used software MATLAB.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.7 no.2
• /
• pp.110-119
• /
• 2007

A new two-dimensional analytical model for dual-material double-gate fully-depleted SOI MOSFET with Pearson-IV type Doping Distribution is presented. An investigation of electrical MOSFET parameters i.e. drain current, transconductance, channel resistance and device capacitance in DM DG FD SOI MOSFET is carried out with Pearson-IV type doping distribution as it is essential to establish proper profiles to get the optimum performance of the device. These parameters are categorically derived keeping view of potential at the center (${\phi}_c$) of the double gate SOI MOSFET as it is more sensitive than the potential at the surface (${\phi}_s$). The proposed structure is such that the work function of the gate material (both sides) near the source is higher than the one near the drain. This work demonstrates the benefits of high performance proposed structure over their single material gate counterparts. The results predicted by the model are compared with those obtained by 2D device simulator ATLAS to verify the accuracy of the proposed model.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.07a
• /
• pp.288-291
• /
• 2004

Due to the charge compensation effect, SOI(Silicon-On-Insulator) LIGBT with dual-epi layer have been found to exhibit both low forward voltage drop and high static breakdown voltage. In this paper, electrical characteristics of the SOI LIGBT with dual-epi structure is presented. Trenched anode structure is employed to obtain uniform current flowlines and shorted anode structure also employed to prevent the fast latch-up. Latching current density of the proposed LIGBT with $T_1=T_2=2.5{\mu}m,\;N_1=7{\times}10^{15}/cm^3,\;N_2=3{\times}10^{15}/cm^3$ is $800A/cm^2$ and breakdown voltage is 125V while latching current density and breakdown voltage of the conventional LIGBT is $700A/cm^2$ and 55V.

• Transactions of the Korean Society of Mechanical Engineers B
• /
• v.40 no.2
• /
• pp.111-117
• /
• 2016

The primary concern of this research is to examine the phonon mean free path (MFP) spectrum contribution to heat conduction. The size effect of materials is determined by phonon MFP, and the size effect appears when the phonon MFP is similar to or less than the characteristic length of materials. Therefore, knowledge of the phonon MFP is essential to increase or decrease the heat conduction of a material for engineering applications, such as micro/nanosystems. In this study, frequency dependence of the phonon transport is considered using the Boltzmann transport equation based on a full phonon dispersion model. Additionally, the phonon MFP spectrums of in-plane and out-of-plane heat transport are investigated by varying the film thickness of the silicon layer from 41 nm to 177 nm. This will increase the understanding of anisotropic heat conduction in a SOI (Silicon-on-Insulator) transistor.

• Journal of Sensor Science and Technology
• /
• v.30 no.6
• /
• pp.395-407
• /
• 2021

The effect of the specifications of a silicon-on-insulator vertical slot optical waveguide on the sensitivity of homogeneous and surface sensing configurations for TE and TM polarization, respectively, was systematically analyzed using numerical software. The specifications were optimized based on the confinement factor and transmission power of the TE-guided mode distributed in the slot. The waveguide sensitivities of homogeneous and surface sensing were calculated according to the specifications of the optimized slot optical waveguide.

• Proceedings of the IEEK Conference
• /
• 2004.06b
• /
• pp.355-358
• /
• 2004

In this work, N-LDMOSFET(Lateral Double diffused MOSFET) was designed and fabricated on SOI(Silicon-On-Insulator) substrate, for such applications as motor controllers and high voltage switches, fuel injection controller systems in automobile and SSR(Solid State Rexay)etc. The LDMOSFET was designed to overcome the floating body effects that appear in the conventional thick SOI MOS structure by adding p+ region in source region. Also, RESURF(Reduced SURface Field) structure was proposed in this work in order to reduce a large on-resistance of LDMOSFET when operated keeping high break down voltage. Breakdown voltage was 268v in off-state ($V_{GS}$=OV) at room temperature in $22{\mu}m$ drift length LDMOSFET. When 5V of $V_{GS}$ and 30V of $V_{DS}$ applied, the on resistance(Ron), the transcon ductance($G_m$) and the threshold voltage($V_T$) was 1.76k$\Omega$, 79.7uA/V and 1.85V respectively.

• Journal of the Microelectronics and Packaging Society
• /
• v.12 no.3 s.36
• /
• pp.187-196
• /
• 2005

MEMS devices such as a vibratory gyroscope often suffer from a lower yield rate due to fabrication errors and the external stress. In the decoupled vibratory gyroscope, the main factor that determines the yield rate is the frequency difference between the sensing and driving modes. The gyroscope, fabricated with SOI (Silicon-On-Insulator) wafer and packaged using the anodic bonding, has a large wafer bowing caused by thermal expansion mismatch as well as non-uniform surfaces of the structures caused by the notching effect. These effects result in large distribution in the frequency difference, and thereby a lower yield rate. To improve the yield rate we propose a packaged SiOG (Silicon On Glass) technology. It uses a silicon wafer and two glass wafers to minimize the wafer bowing and a metallic membrane to avoid the notching. In the packaged SiOG gyroscope, the notching effect is eliminated and the warpage of the wafer is greatly reduced. Consequently the frequency difference is more uniformly distributed and its variation is greatly improved. Therefore we can achieve a more robust vibratory MEMS gyroscope with a higher yield rate.

• Proceedings of the Korean Magnestics Society Conference
• /
• 2004.12a
• /
• pp.31-32
• /
• 2004

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2010.06a
• /
• pp.353-353
• /
• 2010

본 논문에서는 소스와 드레인의 형성에 있어서 implantation 이 아닌 silicide를 형성시켜서 최고온도 $500^{\circ}C$가 넘지않는 저온공정을 실현하였고, silicon-on-insulator (SOI) 기판이 아닌 solid phase crystallization (SPC) 결정화 방법을 이용하여 결정화 시킨 SPC-TFT 기판을 사용하였다. Silicide 의 형성은 pt를 증착하여 furnace에서 열처리를 실시하여 형성하였다.

• Progress in Superconductivity
• /
• v.11 no.1
• /
• pp.36-41
• /
• 2009

Superconducting quantum phenomena are getting attention from the field of metrology area. Following its first successful application of Josephson effect to voltage standard, piconewton force standard was suggested as a candidate for the next application of superconducting quantum effects in metrology. It is predicted that a micron-sized superconducting Nb ring in a strong magnetic field gradient generates a quantized force of the order of sub-piconewtons. In this work, we studied the design and fabrication of Nb superconducting quantum interference device (SQUID) on an ultra-thin silicon cantilever. The Nb SQUID and electrodes were structured on a silicon-on-insulator (SOI) wafer by dc magnetron sputtering and lift-off lithography. Using the resulting SOI wafer, we fabricated V-shaped and parallel-beam cantilevers, each with a $30-{\mu}m$-wide paddle; the length, width, and thickness of each cantilever arm were typically $440{\mu}m,\;4.5{\mu}m$, and $0.34{\mu}m$, respectively. However, the cantilevers underwent bending, a technical difficulty commonly encountered during the fabrication of electrical circuits on ultra-soft mechanical substrates. In order to circumvent this difficulty, we controlled the Ar pressure during Nb sputtering to minimize the intrinsic stress in the Nb film and studied the effect of residual stress on the resultant device.