• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.63-63
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• 2003

The nanotopography of silicon wafers has emerged as an important factor in the STI process since it affects the post-CMP thickness deviation (OTD) of dielectric films. Ceria slurry with surfactant is widely applied to STI-CMP as it offers high oxide-to-nitride removal selectivity. Aiming to control the nanotopography impact through ceria slurry characteristics, we examhed the effect of surfactant concentration and abrasive size on the nanotopography impact. The ceria slurries for this study were produced with cerium carbonate as the starting material. Four kinds of slurry with different size of abrasives were prepared through a mechanical treatment The averaged abrasive size for each slurry varied from 70 nm to 290 nm. An anionic organic surfactant was added with the concentration from 0 to 0.8 wt %. We prepared commercial 8 inch silicon wafers. Oxide Shu were deposited using the plasma-enhanced tetra-ethyl-ortho-silicate (PETEOS) method, The films on wafers were polished on a Strasbaugh 6EC. Film thickness before and after CMP was measured with a spectroscopic ellipsometer, ES4G (SOPRA). The nanotopogrphy height of the wafer was measured with an optical interferometer, NanoMapper (ADE Phase Shift)

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.364.1-364.1
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• 2014

고효율 태양전지로 가기 위해서는 태양전지의 후면 패시베이션은 중요한 역할을 한다. 후면 패시베이션 막으로 사용되는 $Al_2O_3$ 막은 $Al_2O_3/Si$ 계면에서 높은 화학적 패시베이션과 Negative Fixed Charge를 가지고 있어 적합한 Barrier막으로 여겨진다. 하지만 이후에 전면 Metal paste의 소성 공정에 의해 $800^{\circ}C$이상 온도를 올려주게 됨에 따라 $Al_2O_3$ 막 내부에 결합되어 있던 수소들이 방출되어 blister가 생성되고 막 질은 떨어지게 된다. 우리는 blister가 생성되는 것을 방지하기 위한 방법으로 PECVD 장비로 SiNx를 증착하는 공정 중에 $N_2O$ 가스를 첨가하여 SiON 막을 증착하였다. SiON막은 $N_2O$가스량을 조절하여 막의 특성을 변화시키고 변화에 따라 소성시 막에 미치는 영향에 대하여 조사하였다. 공정을 위해 $156{\times}156mm2$, $200{\mu}m$, $0.5-3.0{\Omega}{\cdot}cm$ and p-type 단결정 실리콘 웨이퍼를 사용하였고, $Al_2O_3$ 막을 올리기 전에 RCA Cleaning 실행하였다. ALD 장비를 통해 $Al_2O_3$ 막을 10nm 증착하였고 RF-PECVD 장비로 SiNx막과 SiON막을 80nm 증착하였다. 소성로에서 $850^{\circ}C$ ($680^{\circ}C$) 5초동안 소성하고 QSSPC를 통해 유효 반송자 수명을 알아보았다.

• 정보저장시스템학회:학술대회논문집
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• 2005.10a
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• pp.22-25
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• 2005

In this research, a wafar-level transfer method of cantilever array on a conventional CMOS circuit has been developed for high density probe-based data storage. The transferred cantilevers were silicon nitride ($Si_3N_4$) cantilevers integrated with poly silicon heaters and piezoelectric sensors, called thermo-piezoelectric $Si_3N_4$ cantilevers. In this process, we did not use a SOI wafer but a conventional p-type wafer for the fabrication of the thermo-piezoelectric $Si_3N_4$ cantilever arrays. Furthermore, we have developed a very simple transfer process, requiring only one step of cantilever transfer process for the integration of the CMOS wafer and cantilevers. Using this process, we have fabricated a single thermo-piezoelectric $Si_3N_4$ cantilever, and recorded 65nm data bits on a PMMA film and confirmed a charge signal at 5nm of cantilever deflection. And we have successfully applied this method to transfer 34 by 34 thermo-piezoelectric $Si_3N_4$ cantilever arrays on a CMOS wafer. We obtained reading signals from one of the cantilevers.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.151-151
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• 2010

In this paper, the electrically properties of nonvolatile memory (NVM) using multi-stacks gate insulators of oxide-nitride-oxynitride (ONOn) and active layer of the low temperature polycrystalline silicon (LTPS) were investigated. From hydrogenated amorphous silicon (a-Si:H), the LTPS thin films with high crystalline fraction of 96% and low surface's roughness of 1.28 nm were fabricated by the metal induced crystallization (MIC) with annealing conditions of $650^{\circ}C$ for 5 hours on glass substrates. The LTPS thin film transistor (TFT) or the NVM obtains a field effect mobility of ($\mu_{FE}$) $10\;cm^2/V{\cdot}s$, threshold voltage ($V_{TH}$) of -3.5V. The results demonstrated that the NVM has a memory window of 1.6 V with a programming and erasing (P/E) voltage of -14 V and 14 V in 1 ms. Moreover, retention properties of the memory was determined exceed 80% after 10 years. Therefore, the LTPS fabricated by the MIC became a potential material for NVM application which employed for the system integration of the panel display.

• Journal of the Korean Vacuum Society
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• v.22 no.4
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• pp.188-192
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• 2013

Many studies have been conducted for preventing from diffusion between silicon wafer and metallic thin film due to a decrease of line-width and multi-layer thin film for miniaturization and high integration of semiconductor. This paper has focused on the nano-mechanical property of diffusion barrier which sample is prepared for various gas flow rate of nitrogen with tungsten (W) base from 2.5 to 10 sccm. The deposition rate, resistivity and crystallographic properties were measured by a ${\beta}$-ray back-scattering spectroscopy, 4-point probe and x-ray diffraction (XRD), respectively. We also has investigated the nano-mechanical property using the nano-indenter. As a result, the surface hardness of W-N thin film was increased rapidly from 10.07 to 15.55 GPa when the nitrogen gas flow was increased from 2.5 to 5 sccm. And the surface hardness of W-N thin film had 12.65 and 12.77 GPa at the nitrogen gas flow of 7.5 and 10 sccm respectively. These results were decreased by the comparison with the W-N thin film at nitrogen gas flow of 5 sccm. It was inferred that these severe changes were caused by the stoichiometric difference between the crystalline and amorphous state in W-N thin film. In addition, these results were caused by increased compressive stress.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.206-207
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• 2009

PECVD를 이용하여 상온에서 Silicon nitride 박막을 제조하였다. 그리고 증착 중에 non-invasive ion energy analyzer를 이용하여 이온에너지와 이온에너지 flux룰 측정하였다. PECVD의 소스 파워는 500W, 바이어스 파워 100W으로 고정하고 주파수 250Hz으로 고정된 상태에서 펄스를 인가하여 duty ratio를 30-100%까지 변화시켰다. 작은 duty ratio 범위 (30-70%)에서 duty ratio가 감소할 때, 이온에너지와 이온에너지의 비가 감소하였다. 이 때 감소되는 굴절률은 저이온에너지 변수와 강한 연관성을 지니고 있었다. 굴절률은 1.65-2.46 사이에서 변화하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.695-698
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• 2006

The photosensitive poly-siloxane material used as the passivation layers for the conventional back channel etched (BCE) thin film transistors (TFTs) has been investigated. Through the organic material, the TFT array fabrication process can be reduced and higher aperture ratio can be achieved for higher LCD panel performance. The interface between the organic passivation layer and the back channel of the amorphous active region has been improved by the back channel oxygen treatment and the devices exhibits lower leakage current than the conventional silicon nitride passivation layer of BCE TFTs. The leakage currents between Indium-tin-oxide (ITO) pixels and the TFT devices and its mechanism have also been investigated in this paper.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1406-1408
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• 2006

Plastic substrate for flexible TFT LCD is developed. The gas barrier, optical properties and conductivity in the substrate is improved through depositing silicon oxide/nitride layer and ITO layer, coating polymer layer on plastic film by sputtering process and wet coating process. The whole production process of the plastic substrate is guaranteed the productivity by using roll to roll process.

• Electrical & Electronic Materials
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• v.8 no.1
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• pp.21-26
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• 1995

Highly sensitive and mechanically stable gas sensors have been fabricated using the microfabrication and micromaching techniques. The sensing material used to detect the offensive trimethylarnine ((CH$_{3}$)$_{3}$N) gas is 6 wt% $Al_{2}$O$_{3}$-doped, 1000.angs.-thick ZnO deposited by r. f. magnetron sputtering. The optimum operating temperature of the sensor is 350.deg.C and the corresponding heater power is about 85mW. Excellent thermal insulation is achieved by the use of a double-layer structure of 0.2.mu.m -thick silicon nitride and 1.4.mu.m-thick phosphosilicate glass(PSG) prepared by low pressure chemical vapor deposition(LPCVD) and atmospheric pressure chemical vapor deposition(APCVD), respectively. The sensors are mechanically stable enough to endure at least 43, 200 heat cycles between room temperature and 350.deg. C.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.743-746
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• 2007

본 연구에서는 LCD, 이미지 센서 등의 개별 소자인 비정질 실리콘 박막 트랜지스터에서 게이트 유전층 및 절연층으로 사용되는 비정질 질화 실리콘 박막을 사일렌$(SiH_4)$ 및 암모니아가스를 사용해서 PECVD(Plasma Enhanced Chemical Vapor Deposition) 진공 증착장비로 최적의 비정질질화실리콘 박막 증착 조건을 확립한다. 먼저 반응실의 진공도, rf 전력 , $SiH_4$ 및 질소 그리고 암모니아가스의 flow rate를 변화시키면서 형성된 박막의 특성을 조사한다. 계속해서 다른 변수를 고정시킨 상태에서 rf 전력을 변화시키고 다음에는 반응실의 진공도 등을 변화시켜 최적의 증착조건을 확립한다. 이렇게 확립된 증착조건을 사용하여 비정질질화실리콘박막을 제작하여 특성을 측정한결과 우수한 성능을 나타냈음을 확인하였다.