• Korean Journal of Materials Research
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• v.20 no.12
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• pp.649-653
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• 2010

In this paper, double texturization of multi crystalline silicon solar cells was studied with laser and reactive ion etching (RIE). In the case of multi crystalline silicon wafers, chemical etching has problems in producing a uniform surface texture. Thus various etching methods such as laser and dry texturization have been studied for multi crystalline silicon wafers. In this study, laser texturization with an Nd:$YVO_4$ green laser was performed first to get the proper hole spacing and $300{\mu}m$ was found to be the most proper value. Laser texturization on crystalline silicon wafers was followed by damage removal in acid solution and RIE to achieve double texturization. This study showed that double texturization on multi crystalline silicon wafers with laser firing and RIE resulted in lower reflectance, higher quantum yield and better efficiency than that process without RIE. However, RIE formed sharp structures on the silicon wafer surfaces, which resulted in 0.8% decrease of fill factor at solar cell characterization. While chemical etching makes it difficult to obtain a uniform surface texture for multi crystalline silicon solar cells, the process of double texturization with laser and RIE yields a uniform surface structure, diminished reflectance, and improved efficiency. This finding lays the foundation for the study of low-cost, high efficiency multi crystalline silicon solar cells.

• Bulletin of the Korean Chemical Society
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• v.35 no.5
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• pp.1523-1528
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• 2014

Silicon quantum dots (Si QDs) were synthesized by etching silicon nanopowder with aqueous hydrofluoric acid (HF) and nitric acid ($HNO_3$). Then, the hydride-terminated Si QDs (H-Si QDs) were functionalized by 1- octadecene (ODE). By only controlling the etching time, the maximum luminescence peak of octadecylterminated Si QDs (ODE-Si QDs) was tuned from 404 nm to 507 nm. The average optical gap was increased from 2.60 eV (ODE-Si QDs-5 min) for 5 min of etching to 3.20 eV (ODE-Si QDs-15 min) for 15 min of etching, and to 3.40 eV (ODE-Si QDs-30 min) for 30 min of etching. The electron affinities (EA), ionization potentials (IP), and quasi-particle gap (${\varepsilon}^{qp}_{gap}$) of the Si QDs were determined by cyclic voltammetry (CV). The quasi-particle gaps obtained from the CV were in good agreement with the average optical gap values from UV-vis absorption. In the case of the ODE-Si QDs-30 min sample, the difference between the quasi-particle gap and the average optical gap gives the electron-hole Coulombic interaction energy. The additional electronic levels of the ODE-Si QDs-30 min and ODE-Si QDs-15 min samples determined by the CV results are interpreted to have originated from the Si=O bond terminating Si QD.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.11a
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• pp.44.2-44.2
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• 2009

Polycrystalline materials suchas yttria and alumina have been applied as a plasma resisting material for the plasma processing chamber. However, polycrystal line material may easily generate particles and the particles are sources of contamination during the plasma enhanced process. Amorphous material can be suitable to prevent particle generation due to absence of grain-boundaries. We manufactured nitrogen-containing $SiO_2-Al_2O_3-Y_2O_3$ based glasses with various contents of silicon and fixed nitrogen content. The thermal properties, mechanical properties and plasma etching rate were evaluated and compared for the different composition samples. The plasma etching behavior was estimated using XPS with depth profiling. From the result, the plasma etching rate highly depends on the silicon content and it may results from very low volatile temperature of SiF4 generated during plasma etching. The silicon concentration at the plasma etched surface was very low besides the concentration of yttrium and aluminum was relatively high than that of silicon due to high volatile temperature of fluorine compounds which consisted with aluminum and yttrium. Therefore, we conclude that the samples having low silicon content should be considered to obtain low plasma etching rate for the plasma resisting material.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.5
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• pp.353-357
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• 2010

Recently, silicon etching have received much attention for display industry, nano imprint technology, silicon photonics, and MEMS application. After the etching process, removing of etch mask and residue of sidewall is very important. The investigation of the etched mask removing was carried out by using the ashing, HF dipping and acid cleaning process. Experiment shows that oxygen component of reactive gas and photoresist react with silicon and converting them into the mask fence. It is very difficult to remove by using ashing or acid cleaning process because mask fence consisted of Si and O compounds. However, dilute HF dipping is very effective process for SiOx layer removing. Finally, we found optimized condition for etched mask removing.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.351-354
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• 2004

This work presents a simple and cost-effective approach for maskless fabrication of positive-tone silicon master for the replica molding of hyperfine elastomeric channel. Positive-tone silicon masters were fabricated by a maskless fabrication technique using the combination of nanoscratch by Nanoindenter ⓡ XP and XOH wet etching. Grooves were machined on a silicon surface coated with native oxide by ductile-regime nanoscratch, and they were etched in a 20 wt％ KOH solution. After the KOH etching process, positive-tone structures resulted because of the etch-mask effect of the amorphous oxide layer generated by nanoscratch. The size and shape of the positive-tone structures were controlled by varying the etching time (5, 15, 18, 20, 25, 30 min) and the normal loads (1, 5 mN) during nanoscratch. Moreover, the effects of the Berkovich tip alignment (0, 45$^{\circ}$) on the deformation behavior and etching characteristic of silicon material were investigated.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.1038-1041
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• 2003

In the paper, we investigated silicon surface microstructures formed by reactive ion etching in hollow cathode system. Wet anisotropic chemical etching technique use to form random pyramidal structure on <100> silicon wafers usually is not effective in texturing of low-cost multicrystalline silicon wafers because of random orientation nature, but High density hollow cathode plasma system illustrates high deposition rate, better film crystal structure, improved etching characteristics. The etched silicon surface is covered by columnar microstructures with diameters form 50 to 100nm and depth of about 500nm. We used $SF_{6}$ and $O_{2}$ gases in HCP dry etch process. This paper demonstrates very high plasma density of $2{\times}10^{12}$ $cm^{-3}$ at a discharge current of 20 mA. Silicon etch rate of 1.3 ${\mu}s/min$. was achieved with $SF_{6}/O_{2}$ plasma conditions of total gas pressure=50 mTorr, gas flow rate=40 sccm, and rf power=200 W. Our experimental results can be used in various display systems such as thin film growth and etching for TFT-LCDs, emitter tip formations for FEDs, and bright plasma discharge for PDP applications. In this paper we directed our study to the silicon etching properties such as high etching rate, large area uniformity, low power with the high density plasma.

• Journal of the Korean Electrochemical Society
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• v.14 no.4
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• pp.191-195
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• 2011

Wet chemical etching methods were utilized to conduct Si surface texturing, which could enhance photoelectrochemical hydrogen generation rate. Two different etching methods tested, which were anisotropic metal-catalyzed electroless etching and isotropic etching. The Si nano-texture that was fabricated by the anisotropic etching showed ~25% increase in photocurrent for H2 generation. The photocurrent enhancement was attributed to the reduced reflection loss at the nano-textured Si surface, which provided a layer of intermediate density between water and the Si substrate.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.7 no.3
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• pp.449-455
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• 1997

The anisotropic etching behavior of single crystal silicon were studied in aqueous KOH solution. N-type (100) oriented single crystal silicon wafers were used for the study, and the $SiO_2$ layer, whose etching rate is known to be much slower than that of silicon in the KOH solution, was used as a mask for the silicon etching. The silicon etching rate and the etching properties are shown to be a function of etchant temperature uniformity, circulation speed, and circulation direction of the etchant as well as the etchant concentration and the temperature. The etching rate is increased as the temperature is increased from $10\mu \textrm{m}/hr$ to $250\mu \textrm{m}/hr$ in the range of $50^{\circ}C~105^{\circ}C$. Hillock density and height is observed to be correlated with the etchant concentration and the etch temperature. The variation of the hillock density was explained by the ratio between the etching rate of (100) orientation and that of (111) orientation.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.2
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• pp.62-66
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• 2004

This paper investigated the characteristics of a newly developed high density hollow cathode plasma (HCP) system and its application for the etching of silicon wafers. We used SF$_{6}$ and $O_2$ gases in the HCP dry etch process. Silicon etch rate of $0.5\mu\textrm{m}$/min was achieved with $SF_6$$O_2$plasma conditions having a total gas pressure of 50mTorr, and RF power of 100 W. This paper presents surface etching characteristics on a crystalline silicon wafer and large area cast type multicrystlline silicon wafer. The results of this experiment can be used for various display systems such as thin film growth and etching for TFT-LCDs, emitter tip formations for FEDs, and bright plasma discharge for PDP applications.s.

• Journal of the Korean Ceramic Society
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• v.39 no.6
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• pp.570-575
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• 2002

The present tendency of electrical and electronics is concentrated on MEMS devices for advantage of miniaturization, intergration, low electric power and low cost. Therefore it is essential that high aspect ratio and high etch rate by HDP technology development, so that silicon deep trench etching reactions was studied by ICP equipment. Deep trench etching of silicon was investigated as function of platen power, etch step time of etch/passivation cycle time and SF$\_$6/:C$_4$F$\_$8/ flow rate. Their effects on etch profile, scallops, etch rate, uniformity and selectivity were also studied.