• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.239.2-239.2
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• 2016

Numerous studies and approaches have been performed for solar cells to improve their photoelectric conversion efficiencies. Among them, the study for electrode containing transparent conducting oxide (TCO) layers is one of issues as well as for the cell structure based on band theory. In this study, we focused on an interfacial layer between p-type silicon and indium tin oxide (ITO) well-known as TCO materials. According to current-voltage characteristics for the sample with the interfacial layers, the improvement of band alignment between p-type silicon and ITO was observed, and their ohmic properties were enhanced in the proper condition of deposition. To investigate cause of this improvement, spectroscopic ellipsometry and ultraviolet photoelectron spectroscopy were utilized. Using these techniques, band alignment and defect in the band gap were examined. The major materials of the interfacial layer are vanadium oxide and tungsten oxide, which are notable as a hole transfer layer in the organic solar cells. Finally, the interfacial layer was applied to silicon solar cells to see the actual behavior of carriers in the solar cells. In the case of vanadium oxide, we found 10% of improvement of photoelectric conversion efficiencies, compared to solar cells without interfacial layers.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.686-686
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• 2013

Crystalline silicon solar cell is a semiconductor device that converts light into electrical energy. Screen printing is commonly used to form the front/back electrodes in silicon solar cell. Screen printing method is convenient but usually shows high resistance and low aspect ratio, which cause the efficiency decrease in crystalline silicon solar cell. Recently the plating method is applied in c-Si solar cell to reduce the resistance and improve the aspect ratio. In this paper, we investigated the effect of additional electroless Ag plating into screen-printed c-Si solar cell and compared their electrical properties. All wafers used in this experiment were textured, doped, and anti-reflection coated. The electrode formation was performed with screen-printing, followed by the firing step. Aften then we carried out electroless Ag plating by changing the plating time in the range of 20 sec~5 min and light intensity. The light I-V curve and optical microscope were measured with the completed solar cell. As a result, the conversion efficiency of solar cells was increased mainly due to the decreased series resistance.

• 한국신재생에너지학회:학술대회논문집
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• 2009.11a
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• pp.349-349
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• 2009

High quality ZnO:Al films were prepared on glass substrates by in-line RF magnetron sputtering and their surface morphologies were modified by wet-etching process in dilute acid solution to improve optical properties for application to silicon thin film solar cells as front electrode. The as-deposited films show a strong preferred orientation in [001] direction under our experimental conditions. A low resistivity below $5{\times}10^{-4}{\Omega}{\cdot}cm$ and high optical transmittance above 80% in a visible range are achieved in the films deposited at optimized conditions. After wet-etching, the surface morphologies of the films are changed dramatically depending on the deposition conditions, especially working pressure. The optical properties such as total/diffuse transmittance, haze and angular resolved distribution of light are varied significantly with the surface morphology feature, whereas the electrical properties are seldom changed. The cell performances of silicon thin film solar cells fabricated on the textured films are also evaluated in detail with comparison of commercial $SnO_2$:F films.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.100.2-100.2
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• 2012

Surface texturing of crystalline silicon is carried out in alkaline solutions for anisotropic etching that leads to random pyramids of about $10{\mu}m$ in size. Recently textured pyramids size gradually reduced using new solution. In this paper, we investigated that texture pyramids size had an impact on emitter property and front electrode (Ag) contact. To make small (${\sim}3{\mu}m$) and large (${\sim}10{\mu}m$) pyramids size, texturing times control and one side texturing using a silicon nitride film were carried out. Then formation and quality of POCl3-diffused n+ emitter in furnace compare with small and large pyramids by using SEM images, simulation (SILVACO, Athena module) and emitter saturation current density (J0e). After metallization, Ag contact resistance was measured by transfer length method (TLM) pattern. And surface distributions of Ag crystallites were observed by SEM images. Also, performance of cell which is fabricated by screen-printed solar cells is compared by light I-V.

• Transactions on Electrical and Electronic Materials
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• v.16 no.4
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• pp.183-186
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• 2015

This research investigates the impact of charge spreading on the data retention of three-dimensional (3D) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory where the charge trapping layer is shared along the cell string. In order to do so, this study conducts an electrical analysis of the planar SONOS test pattern where the silicon nitride charge storage layer is not isolated but extends beyond the gate electrode. Experimental results from the test pattern show larger retention loss in the devices with extended storage layers compared to isolated devices. This retention degradation is thought to be the result of an additional charge spreading through the extended silicon nitride layer along the width of the memory cell, which should be improved for the successful 3-D application of SONOS flash devices.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.6
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• pp.1123-1127
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• 2009

This paper expands the scope of application of the thin film transistor (TFT) in which it is used as the switching element by making the amorphous silicon TFT with the non-volatile memory device,. It is the thing about the amorphous silicon non-volatile memory device which is suitable to an enlargement and in which this uses the additionally cheap substrate according to the amorphous silicon use. As to, the amorphous silicon TFT non-volatile memory device is comprised of the glass substrates and the gate, which evaporates on the glass substrates and in which it patterns the first insulation layer, in which it charges the gate the floating gate which evaporates on the first insulation layer and in which it patterns and the second insulation layer in which it charges the floating gate, and the active layer, in which it evaporates the amorphous silicon on the second insulation layer the source / drain layer which evaporates the n+ amorphous silicon on the active layer and in which it patterns and the source / drain layer electrode in which it evaporates on the source / drain layer.

• Korean Chemical Engineering Research
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• v.56 no.1
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• pp.139-142
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• 2018

Silicon (Si) is a promising anode material for next-generation lithium ion batteries (LIBs) because of its high capacity of 4,200 mAh/g ($Li_{4.4}Si$ phase). However, the large volume expansion of Si during lithiation leads to electrical failure of electrode and rapid capacity decrease. Generally, a binder is homogeneously mixed with active materials to maintain electrical contact, so that Si needs a particular binding system due to its large volume expansion. Polyvinyl alcohol (PVA) is known to form a hydrogen bond with partially hydrolyzed silicon oxide layer on Si nanoparticles. However, the decrease of its cohesiveness followed by the repeated volume change of Si still remains unsolved. To overcome this problem, we have introduced the electrospinning method to weave active materials in a stable nanofibrous PVA structure, where stresses from the large volume change of Si can be contained. We have confirmed that the capacity retention of Si-based LIBs using electrospun PVA matrix is higher compared to the conservative method (only dissolving in the slurry); the $25^{th}$ cycle capacity retention ratio based on the $2^{nd}$ cycle was 37% for the electrode with electrospun PVA matrix, compared to 27% and 8% for the electrodes with PVdF and PVA binders.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.104-104
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• 2009

Critical dimensions has rapidly shrunk to increase the degree of integration and to reduce the power consumption. However, it is accompanied with several problems like direct tunneling through the gate insulator layer and the low conductivity characteristic of poly-silicon. To cover these faults, the study of new materials is urgently needed. Recently, high dielectric materials like $Al_2O_3$, $ZrO_2$ and $HfO_2$ are being studied for equivalent oxide thickness (EOT). However, poly-silicon gate is not compatible with high-k materials for gate-insulator. To integrate high-k gate dielectric materials in nano-scale devices, metal gate electrodes are expected to be used in the future. Currently, metal gate electrode materials like TiN, TaN, and WN are being widely studied for next-generation nano-scale devices. The TaN gate electrode for metal/high-k gate stack is compatible with high-k materials. According to this trend, the study about dry etching technology of the TaN film is needed. In this study, we investigated the etch mechanism of the TaN thin film in an inductively coupled plasma (ICP) system with $O_2/BCl_3/Ar$ gas chemistry. The etch rates and selectivities of TaN thin films were investigated in terms of the gas mixing ratio, the RF power, the DC-bias voltage, and the process pressure. The characteristics of the plasma were estimated using optical emission spectroscopy (OES). The surface reactions after etching were investigated using X-ray photoelectron spectroscopy (XPS) and auger electron spectroscopy (AES).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.358-361
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• 2002

Self-aligned MOSFETS using a polysilicon gate are widely fabricated in silicon technology. The polysilicon layer acts as a mask for the source and drain implants and does as gate electrode in the final product. However, the usage of polysilicon gate as a self-aligned mask is restricted in fabricating SiC MOSFETS since the following processes such as dopant activation, ohmic contacts are done at the very high temperature to attack the stability of the polysilicon layer. A metal instead of polysilicon can be used as a gate material and even can be used for ohmic contact to source region of SiC MOSFETS, which may reduce the number of the fabrication processes. Co-formation process of metal-source/drain ohmic contact and gate has been examined in the 4H-SiC based vertical power MOSFET At low bias region (<20V), increment of leakage current after RTA was detected. However, the amount of leakage current increment was less than a few tens of ph. The interface trap densities calculated from high-low frequency C-V curves do not show any difference between w/ RTA and w/o RTA. From the C-V characteristic curves, equivalent oxide thickness was calculated. The calculated thickness was 55 and 62nm for w/o RTA and w/ RTA, respectively. During the annealing, oxidation and silicidation of Ni can be occurred. Even though refractory nature of Ni, 950$^{\circ}C$ is high enough to oxidize it. Ni reacts with silicon and oxygen from SiO$_2$ 1ayer and form Ni-silicide and Ni-oxide, respectively. These extra layers result in the change of capacitance of whole oxide layer and the leakage current

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.9
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• pp.566-570
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• 2014

Electrode pattern effects on the capacitive humidity sensor were investigated. The fabrication of the capacitive humidity sensor was formed with three steps. The bottom electrode was formed on the silicon substrate with Pt/Ti thin layer by using shadow mask and e-beam evaporator. The photo sensitive polyimide was formed on the bottom electrode by using photolithography process as a humidity sensitive thin film. The upper electrode was formed on the polyimide thin film with Pt/Ti thin layer by using e-beam evaporator and lift-off method. Three electrode patterns, such as circle, square, and triangle pattern, were used and changed the sizes to investigate the effects. The capacitances of the sensors were decreased 622 to 584 pF with the area decreament of patterns 250,000 to $196,250{\mu}m^2$. From these results, a capacitive humidity sensor with photo sensitive polyimide is expected to be applied to a high sensitive humidity sensor.