• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.30-40
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• 1998

We have calculated ultra-low energy silicon-self ion implantations and silicon damages through classical molecular dynamics simulation using empirical potentials. We tested whether the recently developed Environment-Dependent Interatomic Potential(EDIP) was suitable for ultra low energy ion implantation simulation, and found that point defects formation energies were in good agreement with other theoretical calculations, but the calculated vacancy migration energy was overestimated. Most of the damages that are produced by collision cascades are concentrated into amorphous-like pockets. Also, We upgraded MDRANGE code for silicon ion implantation process simulation. We simulated ultra-low energy boron ion implantation, 200eV, 500eV, and 1000eV respectively, and calculated boron profiles with silicon substrate temperature and tilt angle. We investigated that below 1000eV, channeling effect must be considered.

• Proceedings of the KIEE Conference
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• 1998.11c
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• pp.723-725
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• 1998

STI CMP process are substituting gradually for LOCOS(Local Oxidation of Silicon) process to be available below sub-0.5um technology and to get planarized. The other hand, STI CMP process(especially STI CMP with RIE etch back process) has some kinds of defect like Nitride residue, Torn Oxide defect, etc. In this paper, we studied how to reduce Torn Oxide defects after STI CMP with RIE etch back process. Although Torn Oxide defects which occur on Oxide on Trench area is not deep and not sever, Torn oxide defects on Moat area is sometimes very deep and makes the yield loss. We did test on pattern wafers witch go through Trench process, APCVD process, and RIE etch back process by using an REC 472 polisher, IC1000/SUV A4 PAD and KOH base slurry to reduce the number of torn defects and to study what is the root causes of torn oxide defects.

• Korean Journal of Materials Research
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• v.14 no.6
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• pp.413-419
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• 2004

Recently, Silicon On Insulator (SOI) devices emerged to achieve better device characteristics such as higher operation speed, lower power consumption and latch-up immunity. Nevertheless, there are many detrimental defects in SOI wafers such as hydrofluoric-acid (HF)-defects, pinhole, islands, threading dislocations (TD), pyramid stacking faults (PSF), and surface roughness originating from quality of buried oxide film layer. Although the number of defects in SOI wafers has been greatly reduced over the past decade, the turn over of high-speed microprocessors using SOI wafers has been delayed because of unknown defects in SOI wafers. A new characterization method is proposed to investigate the crystalline quality, the buried oxide integrity and some electrical parameters of bonded SOI wafers. In this study, major surface defects in bonded SOI are reviewed using HF dipping, Secco etching, Cu-decoration followed by focused ion beam (FIB) and transmission electron microscope (TEM).

• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.35-40
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• 2017

Aluminium alloys have been used widely since hundreds of years in automotive joining. Silicon is an excellent alloying element that increases the fluidity, depresses the melting temperature and prevents shrinkage defects during solidification, and is cost effective raw material. In recent few decades, research on cast Al-Si alloys has been expanding globally in military, automobile and aerospace industries. These alloys are good wear and corrosion resistant which depends on processing parameters and service conditions. However, the formation of big Si-needles in Al-Si alloys is a serious issue in joining industries. Silicon modification treatments are generally carried out to improve their durability and strength. This paper covers an elaborative study of various Al-Si alloys, the modification strategies to refine the Si-needles, effect of processing parameters and joining characteristics for automotive applications.

• ETRI Journal
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• v.36 no.2
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• pp.301-308
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• 2014

Three-dimensional integration technology results in area savings, platform power savings, and an increase in performance. Through-silicon via (TSV) assembly and manufacturing processes can potentially introduce defects. This may result in increases in manufacturing and test costs and will cause a yield problem. To improve the yield, spare TSVs can be included to repair defective TSVs. This paper proposes a new built-in self-test feature to identify defective TSV channels. For defective TSVs, this paper also introduces dynamic self-repair architectures using code-based and hardware-mapping based repair.

• Korean Journal of Materials Research
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• v.3 no.5
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• pp.482-496
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• 1993

Radiation damage and contamination of silicons etched in the $CF_4+H_2$ and $CHF_3$ magnetron discharges have been characterized using Schottky diode characteristics, TEM, AES, and SIMS as a function of applied magnetic field strength. It turned out that, as the magnetic field strength increased, the radiation damage measured by cross sectional TEM and by leakage current of Schottky diodes decreased colse to that of wet dtched samples especially for $CF_4$ plasma etched samples, For $CF_4+H_2$and $CHF_3$ etched samples, hydrogen from the plasmas introduced extended defects to the silicon and this caused increased leakage current to the samples etched at low magnetic field strength conditions by hydrogen passivation. The thickness of polymer with the increasing magnetic field strength and showed the minimum polymer residue thickness near the 100Gauss where the silicon etch rate was maximum. Also, other contaminants such as target material were found to be minimum on the etched silicon surface near the highest etch rate condition.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.11 no.6
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• pp.259-263
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• 2001

The continuum model of transient point defect dynamics to predict the concentrations of interstitial and vacancy is established by estimating expressions for the thermophysical properties of intrinsic point defects. And the point defect distribution in a Czochralski-grown 200 mm silicon crystal and the location of oxidation-induced stacking fault ring(OiSF-ring) created during the cooling of crystals are calculated by using the numerical analysis. The purpose of this paper is to show that his approach lead to predictions that are consistent with experimental results. Predicted point defect distributions by transient point defect dynamic analysis are in good qualitative agreement with experimental data under widely and abruptly varying crystal pull rates when correlated with the position of the OiSF-ring .

• Journal of the Korean institute of surface engineering
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• v.29 no.5
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• pp.482-486
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• 1996

The progress of microelectronics technology has been requiring agressive developments of device technologies. Also the requirements of the next generation devices is heading to the limits of their functions and materials, and hence asking the very specific silicon wafer such as SOI(Silicon On Insulator) wafer. The talk covers the dome stic and world-wide status of SOI device developments and applications. The presentation will also touch some predictions such as SOI device prgress schedules, impacts on the normal wafer developments, market sizes, SOI wafer prices, and so on. Finally it will cover technical aspects which are silicon oxide conditions for bonding, point defects and, surface contaminations. These points will be hopefully overcome by involved people in microelectronics industry.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.5
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• pp.365-371
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• 2003

We prepared silicon on insulator(SOI) wafer pairs of Si/1800${\AA}$ -SiO$_2$ ∥ 1800${\AA}$ -SiO$_2$/Si using water direct bonding method. Wafer pairs bonded at room-temperature were annealed by a normal furnace system or a fast linear annealing(FLA) equipment, and the micro-structure of bonding interfaces for each annealing method was investigated. Upper wafer of bonded pairs was polished to be 50 $\mu\textrm{m}$ by chemical mechanical polishing(CMP) process to confirm the real application. Defects and bonding area of bonded water pairs were observed by optical images. Electrical and mechanical properties were characterized by measuring leakage current for sweeping to 120 V, and by observing the change of wafer curvature with annealing process, respectively. FLA process was superior to normal furnace process in aspects of bonding area, I-V property, and stress generation.

• Journal of the Korean Society for Nondestructive Testing
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• v.25 no.6
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• pp.459-466
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• 2005

The scanning laser source (SLS) technique has been proposed recently as an effective way to investigate small surface-breaking defects, By monitoring the amplitude and frequency changes of the ultrasound generated as the SLS scans over a defect, the SLS technique has provided enhanced signal-to-noise performance compared to the traditional pitch-catch or pulse-echo ultrasonic methods, An extension of the SLS approach to map defects in microdevices is proposed by bringing both the generator and the receiver to the near-field scattering region of the defects, To facilitate near-field ultrasound measurement, silicon microcantilever probes are fabricated using microfabrication technique and their acoustical characteristics are investigated, Then, both the laser-generated ultrasonic source and the microcantilever probe are used to monitor near-field scattering by a surface-breaking defect.