• Journal of the Korean Ceramic Society
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• v.46 no.5
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• pp.510-514
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• 2009

The microstructure and mechanical behavior of deformed silicon were characterized using transmission electron microscopy and nanoindentation. Structural defects such as stacking faults and dislocations were observed through the diffraction contrast in transmission electron microscopy. The mechanical properties of deformed Si and 111 Si wafer and mechanical behaviors during contact loading were also characterized using nanoindentation. The hardness values of silicon samples were ${\sim}10$ GPa and the elastic modulus were varied with indentation conditions. Elbow or pop-out behaviors were found in load-displacement curves of silicon samples during nanoindentation. Deformed silicon showed 'pop-out' behavior more frequently under the load of 10 mN, which is attributed to the structural defects in deformed silicon.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.164-169
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• 2008

The effects of the antisite related defects on the electronic structure of silica and the gate leakage current have been investigated using first-principles calculations. Energy levels related to the antisite defects in silicon dioxide have been introduced into the bandgap, which are nearly 2.0 eV from the top of the valence band. Combining with the electronic structures calculated from first-principles simulations, tunneling currents through the silica layer with antisite defects have been calculated. The tunneling current calculations show that the hole tunneling currents assisted by the antisite defects will be dominant at low oxide field whereas the electron direct tunneling current will be dominant at high oxide field. With increased thickness of the defect layer, the threshold point where the hole tunneling current assisted by antisite defects in silica is equal to the electron direct tunneling current extends to higher oxide field.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.16 no.2
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• pp.66-70
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• 2006

Various kind of structural defects are observed to be present on the oxidized surface of the silicon crystal which was previously damaged mechanically. The formation of such defects was found to depend on the amount of damage induced and the temperature of thermal oxidation. It was confirmed by the measurement of minority carrier life time that gettering capability decreases as the size of the defects increase. The strained layer which is formed due to smaller amount of damage or lower oxidation temperature believed to has higher capability of gettering over defects like dislocation loops or stacking faults.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.6 no.1
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• pp.11-18
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• 1996

Grown-in defects like OISF and FPD in the large diameter(> 8 inch)of silicon crystal are characterized. It was revealed that the presence of the ring-patterned OISF would deterorate the minority life time of the silicon crystal. Through the cooling experiment from the $1250^{\circ}C$, the nucleation of the OISF was confirmed to follow the homogeneous nucleation and growth process. In addition to OISF nucleus, crystal originated particle, which was known to be closely related with FPD (Flow Pattern Defects), was found to depend on the pulling rate of the crystal. Combination of the lower rate of the pulling and the faster cooling near the $950^{\circ}C$ is proposed to be effective method in reducing the generation of these grown-in defects.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.24 no.5
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• pp.190-195
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• 2014

Because of the temperature gradient occurring during the growth of the ingot with directional solidification method, defects are generated and the residual stress is produced in the ingot. Changing the growth and cooling rate during the crystal growth process will be helpful for us to understand the defects and residual stress generation. The defects and residual stress can affect the properties of wafer. Generally, it was found that the size of grains and twin boundaries are smaller at the top area than at the bottom of the ingot regardless of growth and cooling condition. In addition to that, in the top area of silicon ingot, higher density of dislocation is observed to be present than in the bottom area of the silicon ingot. This observation implies that higher stress is imposed to the top area due to the faster cooling of silicon ingot after solidification process. In the ingot with slower growth rate, dislocation density was reduced and the TTV (Total Thickness Variation), saw mark, warp, and bow of wafer became lower. Therefore, optimum growth condition will help us to obtain high quality silicon ingot with low defect density and low residual stress.

• Transactions on Electrical and Electronic Materials
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• v.5 no.4
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• pp.143-147
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• 2004

Surface defects and bulk defects on SOI wafers are studied. Two new metrologies have been proposed to characterize surface and bulk defects in epitaxial layer transfer (ELTRAN) wafers. They included the following: i) laser scattering particle counter and coordinated atomic force microscopy (AFM) and Cu-decoration for defect isolation and ii) cross-sectional transmission electron microscope (TEM) foil preparation using focused ion beam (FIB) and TEM investigation for defect morphology observation. The size of defect is 7.29 urn by AFM analysis, the density of defect is 0.36 /cm$^2$ at as-direct surface oxide defect (DSOD), 2.52 /cm$^2$ at ox-DSOD. A hole was formed locally without either the silicon or the buried oxide layer (Square Defect) in surface defect. Most of surface defects in ELTRAN wafers originate from particle on the porous silicon.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.20 no.2
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• pp.101-105
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• 2010

Silicon electrode and ring in a plasma etcher those are in contact with harsh plasma suffer from periodic heating and cooling during their lifetime. This causes the silicon components failure due to thermal stress remaining the persistent slip bands (PSBs) on their surfaces. The factors that determine the lifetime of silicon electrode and ring were discussed with respect to silicon ingot. The impurity level and the average defect concentration measured with glow discharge mass spectrometer (GDMS) and microwave photo-conductance decay (${\mu}$-PCD) were compared with the grade of silicon ingots those are divided to slip-free and slip-allowed ingot. Some silp-allowed samples showed planar defects along <110> direction on {001} surface. The role of these defects was suggested from the viewpoint of the lifetime of silicon components.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.25 no.1
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• pp.13-19
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• 2015

Among the various possible factors affecting the Minority Carrier Life Time (MCLT) of the mc-Si crystal, dislocations formed during the cooling period after solidification were found to be a major element. It was confirmed that other defects such as grain boundary or twin boundary were not determinative defects affecting the MCLT because most of these defects seemed to be formed during the solidification period. With a measurement of total thickness variation (TTV) and bow of the silicon wafers, it was found that residual stress remaining in the mc-Si crystal might be another major factor affecting the MCLT. Thus, it is expected that better quality of mc-Si can be grown when the cooling process right after solidification is carried out as slow as possible.

• Korean Journal of Materials Research
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• v.22 no.1
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• pp.8-15
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• 2012

Silicon-based thin film was prepared at room temperature by an electrochemical deposition method and a feasibility study was conducted for its use as an anode material in a rechargeable lithium battery. The growth of the electrodeposits was mainly concentrated on the surface defects of the Cu substrate while that growth was trivial on the defect-free surface region. Intentional formation of random defects on the substrate by chemical etching led to uniform formation of deposits throughout the surface. The morphology of the electrodeposits reflected first the roughened surface of the substrate, but it became flattened as the deposition time increased, due primarily to the concentration of reduction current on the convex region of the deposits. The electrodeposits proved to be amorphous and to contain chlorine and carbon, together with silicon, indicating that the electrolyte is captured in the deposits during the fabrication process. The silicon in the deposits readily reacted with lithium, but thick deposits resulted in significant reaction overvoltage. The charge efficiency of oxidation (lithiation) to reduction (delithiation) was higher in the relatively thick deposit. This abnormal behavior needs to clarified in view of the thickness dependence of the internal residual stress and the relaxation tendency of the reaction-induced stress due to the porous structure of the deposits and the deposit components other than silicon.

• Journal of the Korean Ceramic Society
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• v.32 no.12
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• pp.1377-1382
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• 1995

A high-resolution transmission electron microscopy study on the lattice defects formed in the high energy P ion implanted silicon was carried out on an atomic level. Results show that Lomer dislocations, 60$^{\circ}$perfect dislocations, 60$^{\circ}$ dislocation dipole and extrinsic stacking fault formed in the near Rp of as-implanted specimen. In the annelaed specimens, interstitial Frank loops, 60$^{\circ}$perfect disolations, 60$^{\circ}$dislocation dipoles, stacking faults, precipitates, perfect dislocation loops and <112> rodlike defects existed exclusively near in the Rp with various annealing temperature and time. From these results, it is concluded that extended secondary defects as well as the point defect clusters could be formed without annealing. Even at low temperature annealing such as 55$0^{\circ}C$, small interstitial Frank loops could be formed and precipitates were also formed by $700^{\circ}C$ annealing. The defect band annealed at 100$0^{\circ}C$ for 1 hr could be divided into two regions depending on the distribution of the secondary defects.