• Journal of the Korean Vacuum Society
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• v.13 no.1
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• pp.14-21
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• 2004

It is essential to increase the switching speed of power devices to reduce the energy loss because high frequency is commonly used in power device operation these days. In this work electron irradiation has been conducted to reduce the lifetime of minority carriers and thereby to increase the switching speed of a$p^+- n^-$ junction diode. Effects of electron irradiation on the electrical properties of the diode are reported The switching speed is effectively increased. Also the junction leakages and the forward voltage drop which are anticipated to increase are found to be negligible in the $p^+- n^-$ junction diodes irradiated with the optimum energy and dose. The analysis results of DLTS and C-V profiling indicate that the defects induced by electron irradiation in the silicon substrate are donor-like ones which have the energy levels of 0.284 eV and 0.483 eV. Considering all the experimental results in this study, it might be concluded that electron irradiation is a very useful technique in improving the switching speed and thereby reducing the energy loss of $p^+- n^-$ junction diode power devices.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.1
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• pp.33-40
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• 1992

Several etching phenomena were observed and analyzed in diaphragm process performed on 4-inch (100) Si wafers for sensor application. In case of deep etching to above 300$\mu$m depth, the etch-defects appeared at etched surface could be classified into three categories such as hillocks, reaction products, and white residues. It was known that the hillock had a pyramidal shape or trapizoidal hexahedron structure depending on the density and size of the reaction products. The IR spectra showed that the white residue, which was due to the local over-saturation of Si dissolved in solution, was mostly Si-N-O compounds mixed with a small amount of H and C etc. Also, the difference in both the existence of etch-defects and etch rate distribution over a whole wafer was investigated when the etched surfaces were downward, upward horizontally and erective in etching solutions. The obtained data were analyzed through flow pattern in the etching bath. As the results, the downward and erective postures were favorable in the etch rate uniformity and the etch-defect removal, respectively.

• Journal of Magnetics
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• v.8 no.4
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• pp.138-141
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• 2003

$Ni_{0.65}Zn_{0.35}Fe_2O_4$thin films were prepared by using a sol-gel method. Their crystallographic, dielectric and magnetic properties were investigated as a function of Cu contents by means of an X-ray diffractometer (XRD), X-ray reflectivity, LCZ meter (NF2232), a vibrating sample magnetometer (VSM), and an atomic force microscope (AFM). From typical C-V measurements for $Ni_{0.65}Zn_{0.35}Fe_2O_4$ thin films on p-type silicon substrate, the surface charge density was calculated as 1.4 ${\mu}$C/$m^2$. The dielectric constant evaluated from the capacitance at the accumulation state was 28. The high $H_{c}$ and low $M_{sat}$ at x=0.0 and 0.1 were due to the growth of the ${\alpha}$-$Fe_2O_3$ phase having antiferromagnetic properties. The rapidly decreased $H_{c}$ and increased $M_{sat}$ at x=0.2 and 0.3 can be explained that the ${\alpha}$-$Fe_2O_3$ phases have completely disappeared at x=0.3 and so, non-magnetic defects are minimized. The $M_{sat}$ was slightly decreased and the $H_{c}$ was increased above at x=0.3 because the increase of grain boundary due to smaller grain size acts as defects during magnetization process.

• Korean Journal of Materials Research
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• v.32 no.9
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• pp.396-402
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• 2022

In this study, surface roughness and interfacial defect characteristics were analyzed after forming a high-k oxide film on the surface of a prime wafer and a test wafer, to study the possibility of improving the quality of the test wafer. As a result of checking the roughness, the deviation in the test after raising the oxide film was 0.1 nm, which was twice as large as that of the Prime. As a result of current-voltage analysis, Prime after PMA was 1.07 × 10 A/cm² and Test was 5.61 × 10 A/cm², which was about 5 times lower than Prime. As a result of analyzing the defects inside the oxide film using the capacitance-voltage characteristic, before PMA Prime showed a higher electrical defect of 0.85 × 10¹² cm^-2 in slow state density and 0.41 × 10¹³ cm^-2 in fixed oxide charge. However, after PMA, it was confirmed that Prime had a lower defect of 4.79 × 10¹¹ cm^-2 in slow state density and 1.33 × 10¹² cm^-2 in fixed oxide charge. The above results confirm the difference in surface roughness and defects between the Test and Prime wafer.

• Korean Journal of Materials Research
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• v.6 no.7
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• pp.733-741
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• 1996

In this study MeV Si self ion implantations were done to reveal the intrinsic behavior of defect formation by excluding the possibility of chemical interactions between substrate atoms and dopant ones. Self implantations were conducted using Tandem Accelerator with energy ranges from 1 to 3 MeV. Defect formation by high energy ion implantation has a significant characteristics in that the lattice damage is concentrated near Rp and isolated from the surface. In order to investigate the energy dependence on defect formation, implantation energies were varied from 1 to 3 MeV under a constant dose of $1{\times}10^{15}/cm^2$. RBS channe!ed spectra showed that the depth at which as-implanted damaged layer formed increases as energy increases and that near surface region maintains better crystallinity as energy increases. Cross sectional TEM results agree well with RBS ones. In a TEM image as-implanted damaged layer appears as a dark band, where secondary defects are formed upon annealing. In the case of 2 MeV $Si^+$ self implantation a critical dose for the secondary defect formation was found to be between $3{\times}10^{14}/cm^24$ and $5{\times}10^{14}/cm^2$. Upon annealing the upper layer of the dark band was removed while the bottom part of the dark band did not move. The observed defect behavior by TEM was interpreted by Monte Carlo computer simulations using TRIM-code. SIMS analyses indicated that the secondary defect formed after annealing gettered oxygen impurities existed in silicon.

• Journal of the Korean Society for Nondestructive Testing
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• v.32 no.2
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• pp.122-130
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• 2012

Adhesive bend and shear tests of micro-sized bonded component have been performed to clarify the relationship between effects of heat-treatment on the adhesive strength and the bonded specimen shape using Weibull analysis. Multiple micro-sized SU-8 columns with four different diameters were fabricated on a Si substrate under the same fabrication condition. Heat-treatment can improve both of the adhesive bend and shear strength. The improvement rate of the adhesive shear strength is much larger than that of the adhesive bend strength, because the residual stress, which must change by heat-treatment, should effect more strongly on the shear loading. In case of bend type test, the adhesive bend strength in the smaller diameters (50 and $75\;{\mu}m$) widely vary, because the critical size of the natural defect (micro-crack) should vary more widely in the smaller diameters. In contrast, in case of shear type test, the adhesive shear strengths in each diameter of the columns little vary. This suggests that the size of the natural defects may not strongly influence on the adhesive shear strength. All the result suggests that both of the adhesive bend and shear strengths should be complicatedly affected by heat-treatment and the bonded columnar diameter.

• Proceedings of the KAIS Fall Conference
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• 2002.05a
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• pp.151-154
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• 2002

반도체 소자의 기판 재료로 사용되고 있는 실리콘 웨이퍼는 그 정밀도가 매우 중요하다. 본 연구에서는 균일한 Dopant 농도 분포를 얻을 수 있는 중성자 변환 Doping을 이용하여 실리콘에 인(P)을 Doping하는 연구를 수행하였다. 중성자 변환 Doping, 즉 NTD(Neutron Transmutation Doping)란 원자번호 30인 실리콘 동위원소에 중성자가 조사되면 원자번호 31인 실리콘으로 변환되고, 2.6시간의 반감기를 갖고 decay 되면서 인(P)으로 변하게 되어 실리콘 웨이퍼에 n-type 전도를 갖게 하는 것을 말한다. 본 연구에서는 하나로 원자로를 이용하여 고저항(1000-2000Ωcm) FZ 실리콘 웨이퍼 에 두 개의 조사공에서 중성자 조사하여 저항의 변화를 관찰하였고, 중성자 조사시 발생하는 점결함을 분석하여 점결함이 저항 변화에 미치는 영향을 알아보았다. 중성자 조사 전 이론적 계산에 의해 HTS조사공은 5Ωcm, 20.1Ωcm 이고 IP3조사공은 5Ωcm, 26.5Ωcm, 32.5Ωcm 이었고, 중성자 조사 후 SRP로 측정한 결과 실제 저항값은 HTS-1 2.10Ωcm, HTS-2 7.21Ωcm 이었고, IP-1은 1.79Ωcm, IP-2는 6.83Ωcm, 마지막으로 IP-3는 9.23Ωcm 이었다. DLTS 측정 결과 IP조사공에서 새로운 피의 결을 발견할 수 있었다.

• Journal of Korean Institute of Industrial Engineers
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• v.28 no.1
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• pp.57-62
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• 2002

The semiconductor industry has continuously been looking for the ways to improve yield and to reduce manufacturing cost. The layout modification approach, one of yield enhancement techniques, is applicable to all design styles, but it does not require any additional resources in terms of silicon area. The layout modification method for yield enhancement consists of making local variations in the layout of some layers in such a way that the critical area, and consequently the sensitivity of the layer to point defects, is reduced. Chen and Koren (1995) proposed a greedy algorithm that removes defect sensitive area using via moving, but it is easy to fall into a local minimum. In this paper, we present a via moving algorithm using simulated annealing and enhance yield by diminishing defect sensitive area. As a result, we could decrease the defect sensitive area effectively compared to the greedy algorithm presented by Chen and Koren. We expect that the proposed algorithm can make significant contributions on company profit through yield enhancement.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.1
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• pp.71-74
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• 2006

In this paper, we investigated the characterization of silicon oxide(SiOx) thin film on Ethylene Terephthalate(PET) substrates by e-beam deposition for transparent barrier application. The temperature of chamber increases from $30^{\circ}C$ to $110^{\circ}C$, the roughness increase while the Water vapor transmission rate (WVTR) decreases. Under these conditions, the WVTR for PET can be reduced from a level of $0.57 g/m^2/day$ (bare subtrate) to $0.05 g/m^2/day$ after application of a 200-nm-thick $SiO_2$ coating at 110 C. A more efficient way to improve permeation of PET was carried out by using a double side coating of a 5-${\mu}m$-thick parylene film. It was found that the WVTR can be reduced to a level of $-0.2 g/m^2/day$. The double side parylene coating on PET could contribute to the lower stress of oxide film, which greatly improves the WVTR data. These results indicates that the $SiO_2$ /Parylene/PET barrier coatings have high potential for flexible organic light-emitting diode(OLED) applications.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.3
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• pp.158-166
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• 2001

Based on uniform hot carrier injection (optically assisted electron injection) across the $Si-SiO_2$ interface into the gate insulator of n-channel IGFETs, the threshold voltage shifts associated with electron injection of $1.25{\times}l0^{16}{\;}e/\textrm{cm}^2 between 0.5 and 7 MV/cm were found to decrease from positive to negative values, indicating both a decrease in trap cross section ($E_{ox}{\geq}1.5 MV/cm$) and the generation of FPC $E_{ox}{\geq}5{\;}MV/cm$). It was also found that FNC and large cross section NETs were generated for $E_{ox}{\geq}5{\;}MV/cm$. Continuous, uniform low-field (1MV/cm) electron injection up to $l0^{19}{\;}e/\textrm{cm}^2 is accompanied by a monatomic increase in threshold voltage. It was found that the data could be modeled more effectively by assuming that most of the threshold voltage shift could be ascribed to generated bulk defects which are generated and filled, or more likely, generated in a charged state. The injection method and conditions used in terms of injection fluence, injection density, and temperature, can have a dramatic impact on what is measured, and may have important implications on accelerated lifetime measurements.