• Korean Journal of Materials Research
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• v.8 no.7
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• pp.634-640
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• 1998

A well- shaped trench was investigated in view of the defect distribution along trench sidewall and bottom using high resolution transmission electron microscopy. The trench was formed by HBr plasma and additive gases in magnetically enhanced reactive ion etching system. Adding $0_2$ and other additive gases into HBr plasma makes it possible to eliminate sidewall undercut and lower surface roughness by forming the passivation layer of lateral etching, resulted in the well filled trench with oxide and polysilicon by subsequent deposition. The passivation layer of lateral etching was mainly composed of $SiO_xF_y$ $SiO_xBr_y$ confirmed by chemical analysis. It also affects the generation and distribution of lattice defects. Most of etch induced defects were found in the edge region of the trench bottom within the depth of 10$\AA$. They are generally decreased with the thickness of residue layer and almost disappeared below the uni¬formly thick residue layer. While the formation of crystalline defects in silicon substrate mainly depends on the incident angle and energy of etch species, the region of surface defects on the thickness of residue layer formed during trench etching.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.2
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• pp.85-90
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• 2012

In this paper, we compared and analyzed 3D silicon-oxide-nitride-oxide-silicon (SONOS) multi layer flash memory devices fabricated on nitride or oxide layer, respectively. The device fabricated on nitride layer has inferior electrical properties than that fabricated on oxide layer. However, the device on nitride layer has faster program / erase speed (P/E speed) than that on the oxide layer, although having inferior electrical performance. Afterwards, to find out the reason why the device on nitride has faster P/E speed, 1/f noise analysis of both devices is investigated. From gate bias dependance, both devices follow the mobility fluctuation model which results from the lattice scattering and defects in the channel layer. In addition, the device on nitride with better memory characteristics has higher normalized drain current noise power spectral density ($S_{ID}/I^2_D$>), which means that it has more traps and defects in the channel layer. The apparent hooge's noise parameter (${\alpha}_{app}$) to represent the grain boundary trap density and the height of grain boundary potential barrier is considered. The device on nitride has higher ${\alpha}_{app}$ values, which can be explained due to more grain boundary traps. Therefore, the reason why the devices on nitride and oxide have a different P/E speed can be explained due to the trapping/de-trapping of free carriers into more grain boundary trap sites in channel layer.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2016.11a
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• pp.181-181
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• 2016

Hydrogenated microcrystalline silicon (${\mu}c-Si:H$) films have attracted much attention as materials of the bottom-cells in Si thin film tandem photovoltaics due to their low bandgap and excellent stability against light soaking. However, in PECVD, the source gas $SiH_4$ must be highly diluted by $H_2$, which eventually results in low deposition rate. Moreover, it is known that high-rate ${\mu}c-Si:H$ growth is usually accompanied by a large number of dangling-bond (DB) defects in the resulting films, which act as recombination centers for photoexcited carriers, leading to a deterioration in the device performance. During film deposition, Si nanoparticles generated in $SiH_4$ discharges can be incorporated into films, and such incorporation may have effects on film properties depending on the size, structure, and volume fraction of nanoparticles incorporated into films. Here we report experimental results on the effects of nonoparticles incorporation at the different substrate temperature studied using a multi-hollow discharge plasma CVD method in which such incorporation can be significantly suppressed in upstream region by setting the gas flow velocity high enough to drive nanoparticles toward the downstream region. All experiments were performed with the multi-hollow discharge plasma CVD reactor at RT, 100, and $250^{\circ}C$, respectively. The gas flow rate ratio of $SiH_4$ to $H_2$ was 0.997. The total gas pressure P was kept at 2 Torr. The discharge frequency and power were 60 MHz, 180 W, respectively. Crystallinity Xc of resulting films was evaluated using Raman spectra. The defect densities of the films were measured with electron spin resonance (ESR). The defect density of fims deposited in the downstream region (with nonoparticles) is higher defect density than that in the upstream region (without nanoparticles) at low substrate temperature of RT and $100^{\circ}C$. This result indicates that nanoparticle incorporation can change considerably their film properties depending on the substrate temperature.

• 한국연소학회:학술대회논문집
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• 2005.10a
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• pp.328-336
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• 2005

Effects of surface defect distribution on flame instability during flame-surface interaction are experimentally investigated. To examine the chemical quenching phenomenon, we prepared thermally grown silicon oxide plates with well-defined defect density. Ion implantation was used to control the number of defects, i.e. oxygen vacancies. In an attempt to preferentially remove the oxygen atoms from silicon dioxide surface, argon ions with low energy level from 3keV to 5keV were irradiated at the incident angle of $60^{\circ}C$. Compositional and structural modification of $SiO_2$ induced by low-energy $Ar^+$ ion irradiation has been characterized by Atomic Force Microscopy (AFM) and X-ray Photoelectron Spectroscopy (XPS). The analysis shows that as the ion energy increases, the number of structural defect also increases and non-stoichiometric condition of $SiO_x(x{\le}2)$ plates is enhanced. From the quenching distance measurements, we found out that when the surface temperature is under $300^{\circ}C$, the quenching distance decreases on account of reduced heat loss; as the surface temperature increases over $300^{\circ}C$, however, quenching distance increases despite reduced heat loss effect. Such aberrant behavior is caused by heterogeneous chemical reaction between active radicals and surface defect sites. The higher defect density, the larger quenching distance. This results means that chemical quenching is governed by radical adsorption and can be parameterized by the oxygen vacancy density on the surface.

• Journal of the Korean Ceramic Society
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• v.52 no.6
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• pp.441-448
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• 2015

Silicon carbide (SiC) coatings for tri-isotropic (TRISO) nuclear fuel particles were fabricated using a chemical vapor deposition (CVD) process onto graphite. A micro-tensile-testing system was developed for the mechanical characterization of SiC coatings at high temperatures. The fracture strength of the SiC coatings was characterized by the developed micro-tensile test in the range of $25^{\circ}C$ to $1000^{\circ}C$. Two types of CVD-SiC films were prepared for the micro-tensile test. SiC-A exhibited a large grain size (0.4 ~ 0.6 m) and the [111] preferred orientation, while SiC-B had a small grain size (0.2 ~ 0.3 mm) and the [220] preferred orientation. Free silicon (Si) was co-deposited onto SiC-B, and stacking faults also existed in the SiC-B structure. The fracture strengths of the CVD-SiC coatings, as measured by the high-temperature micro-tensile test, decreased with the testing temperature. The high-temperature fracture strengths of CVD-SiC coatings were related to the microstructure and defects of the CVD-SiC coatings.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.3
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• pp.57-65
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• 2003

In this study, we carry out reliability tests and investigate the failure mechanisms of the anodically bonded wafer level vacuum packaging (WLVP) MEMS gyroscope sensor. There are three failure mechanisms of WLVP: leakage, permeation and out-gassing. The leakage is caused by small dimension of the leak channel through the bonding interface and internal defects. The larger bonding width and the use of single crystalline silicon can reduce the leak rate. Silicon and glass wafer itself generates a large amount of outgassing including $H_2O$, $C_3H_5$, $CO_2$, and organic gases. Epi-poly wafer generates 10 times larger amount of outgassing than SOI wafer. The sandblasting process in the glass increases outgassing substantially. Outgassing can be minimized by pre-baking of the wafer in the vacuum oven before bonding process. An optimum pre-baking temperature of the wafers would be between $400^{\circ}C$ and $500^{\circ}C$.

• Journal of Welding and Joining
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• v.32 no.3
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• pp.68-73
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• 2014

Among through silicon via (TSV) technologies, for replacing Cu filling method, the method of molten solder filling has been proposed to reduce filling cost and filling time. However, because Sn alloy which has a high coefficient of thermal expansion (CTE) than Cu, CTE mismatch between Si and molten solder induced higher thermal stress than Cu filling method. This thermal stress can deteriorate reliability of TSV by forming defects like void, crack and so on. Therefore, we fabricated SiC composite filling material which had a low CTE for reducing thermal stress in TSV. To add SiC nano particles to molten solder, ball-typed SiC clusters, which were formed with Sn powders and SiC nano particles by ball mill process, put into molten Sn and then, nano particle-dispersed SiC composite filling material was produced. In the case of 1 wt.% of SiC particle, the CTE showed a lowest value which was a $14.8ppm/^{\circ}C$ and this value was lower than CTE of Cu. Up to 1 wt.% of SiC particle, Young's modulus increased as wt.% of SiC particle increased. And also, we observed cross-sectioned TSV which was filled with 1 wt.% of SiC particle and we confirmed a possibility of SiC composite material as a TSV filling material.

• Korean Journal of Materials Research
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• v.23 no.10
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• pp.550-554
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• 2013

As continued scaling becomes increasingly difficult, 3D integration has emerged as a viable solution to achieve higher bandwidths and good power efficiency. 3D integration can be defined as a technology involving the stacking of multiple processed wafers containing integrated circuits on top of each other with vertical interconnects between the wafers. This type of 3D structure can improve performance levels, enable the integration of devices with incompatible process flows, and reduce form factors. Through silicon vias (TSVs), which directly connect stacked structures die-to-die, are an enabling technology for future 3D integrated systems. TSVs filled with copper using an electro-plating method are investigated in this study. DC and pulses are used as a current source for the electro-plating process as a means of via filling. A TiN barrier and Ru seed layers are deposited by plasma-enhanced atomic layer deposition (PEALD) with thicknesses of 10 and 30 nm, respectively. All samples electroplated by the DC current showed defects, even with additives. However, the samples electroplated by the pulse current showed defect-free super-filled via structures. The optimized condition for defect-free bottom-up super-filling was established by adjusting the additive concentrations in the basic plating solution of copper sulfate. The optimized concentrations of JGB and SPS were found to be 10 and 20 ppm, respectively.

• Journal of Powder Materials
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• v.28 no.1
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• pp.51-58
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• 2021

The conversion of carbon preforms to dense SiC by liquid infiltration is a prospectively low-cost and reliable method of forming SiC-Si composites with complex shapes and high densities. Si powder was coated on top of a 2.0wt.% Y2O3-added carbon preform, and reaction bonded silicon carbide (RBSC) was prepared by infiltrating molten Si at 1,450℃ for 1-8 h. Reactive sintering of the Y2O3-free carbon preform caused Si to be pushed to one side, thereby forming cracking defects. However, when prepared from the Y2O3-added carbon preform, a SiC-Si composite in which Si is homogeneously distributed in the SiC matrix without cracking can be produced. Using the Si + C → SiC reaction at 1,450℃, 3C and 6H SiC phases, crystalline Si, and Y2O3 were generated based on XRD analysis, without the appearance of graphite. The RBSC prepared from the Y2O3-added carbon preform was densified by increasing the density and decreasing the porosity as the holding time increased at 1,450℃. Dense RBSC, which was reaction sintered at 1,450℃ for 4 h from the 2.0wt.% Y2O3-added carbon preform, had an apparent porosity of 0.11% and a relative density of 96.8%.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.191.2-191.2
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• 2015

Details of carrier dynamics in self-assembled quantum dots (QDs) with a particular attention to nonradiative processes are not only interesting for fundamental physics, but it is also relevant to performance of optoelectronic devices and the exploitation of nanocrystals in practical applications. In general, the possible processes in such systems can be considered as radiative relaxation, carrier transfer between dots of different dimensions, Auger nonradiactive scattering, thermal escape from the dot, and trapping in surface and/or defects states. Authors of recent studies have proposed a mechanism for the carrier dynamics of time-resolved photoluminescence CdTe (a type II-VI QDs) systems. This mechanism involves the activation of phonons mediated by electron-phonon interactions. Confinement of both electrons and holes is strongly dependent on the thermal escape process, which can include multi-longitudinal optical phonon absorption resulting from carriers trapped in QD surface defects. Furthermore, the discrete quantized energies in the QD density of states (1S, 2S, 1P, etc.) arise mainly from ${\delta}$-functions in the QDs, which are related to different orbitals. Multiple discrete transitions between well separated energy states may play a critical role in carrier dynamics at low temperature when the thermal escape processes is not available. The decay time in QD structures slightly increases with temperature due to the redistribution of the QDs into discrete levels. Among II-VI QDs, wide-gap CdZnTe QD structures characterized by large excitonic binding energies are of great interest because of their potential use in optoelectronic devices that operate in the green spectral range. Furthermore, CdZnTe layers have emerged as excellent candidates for possible fabrication of ferroelectric non-volatile flash memory. In this study, we investigated the optical properties of CdZnTe/ZnTe QDs on Si substrate grown using molecular beam epitaxy. Time-resolved and temperature-dependent PL measurements were carried out in order to investigate the temperature-dependent carrier dynamics and the activation energy of CdZnTe/ZnTe QDs on Si substrate.