DOI QR코드

DOI QR Code

The 1/f Noise Analysis of 3D SONOS Multi Layer Flash Memory Devices Fabricated on Nitride or Oxide Layer

산화막과 질화막 위에 제작된 3D SONOS 다층 구조 플래시 메모리소자의 1/f 잡음 특성 분석

  • Lee, Sang-Youl (Department of Electronics Engineering, Chungnam National University) ;
  • Oh, Jae-Sub (Nano Process Technology Team, National Nanofab Center) ;
  • Yang, Seung-Dong (Department of Electronics Engineering, Chungnam National University) ;
  • Jeong, Kwang-Seok (Department of Electronics Engineering, Chungnam National University) ;
  • Yun, Ho-Jin (Department of Electronics Engineering, Chungnam National University) ;
  • Kim, Yu-Mi (Department of Electronics Engineering, Chungnam National University) ;
  • Lee, Hi-Deok (Department of Electronics Engineering, Chungnam National University) ;
  • Lee, Ga-Won (Department of Electronics Engineering, Chungnam National University)
  • 이상율 (충남대학교 전자전파정보통신공학과) ;
  • 오재섭 (나노종합팹센터 CMOS 소자팀) ;
  • 양승동 (충남대학교 전자전파정보통신공학과) ;
  • 정광석 (충남대학교 전자전파정보통신공학과) ;
  • 윤호진 (충남대학교 전자전파정보통신공학과) ;
  • 김유미 (충남대학교 전자전파정보통신공학과) ;
  • 이희덕 (충남대학교 전자전파정보통신공학과) ;
  • 이가원 (충남대학교 전자전파정보통신공학과)
  • Received : 2012.01.09
  • Accepted : 2012.01.24
  • Published : 2012.02.01

Abstract

In this paper, we compared and analyzed 3D silicon-oxide-nitride-oxide-silicon (SONOS) multi layer flash memory devices fabricated on nitride or oxide layer, respectively. The device fabricated on nitride layer has inferior electrical properties than that fabricated on oxide layer. However, the device on nitride layer has faster program / erase speed (P/E speed) than that on the oxide layer, although having inferior electrical performance. Afterwards, to find out the reason why the device on nitride has faster P/E speed, 1/f noise analysis of both devices is investigated. From gate bias dependance, both devices follow the mobility fluctuation model which results from the lattice scattering and defects in the channel layer. In addition, the device on nitride with better memory characteristics has higher normalized drain current noise power spectral density ($S_{ID}/I^2_D$>), which means that it has more traps and defects in the channel layer. The apparent hooge's noise parameter (${\alpha}_{app}$) to represent the grain boundary trap density and the height of grain boundary potential barrier is considered. The device on nitride has higher ${\alpha}_{app}$ values, which can be explained due to more grain boundary traps. Therefore, the reason why the devices on nitride and oxide have a different P/E speed can be explained due to the trapping/de-trapping of free carriers into more grain boundary trap sites in channel layer.

Keywords

References

  1. The International Technology Roadmap for Semiconductors, 36 (2001).
  2. J. Bu and M. H. White, Solid State Electron., 45, 113 (2001). https://doi.org/10.1016/S0038-1101(00)00232-X
  3. J. K. Park, S. D. Yang, H. J. Yun, K. S. Jeong, Y. M. Kim, J. S. Oh, H. D. Lee, and G. W. Lee, J. Korean Phys. Soc., 58, 1407 (2011). https://doi.org/10.3938/jkps.58.1407
  4. Y. Sun, H. Y. Yu, N. Singh, N. S. Shen, G. Q. Lo, and D. L. Kwong, IEEE Electron Device Lett., 31, 390 (2010). https://doi.org/10.1109/LED.2010.2041745
  5. S. H. Jeon, J. H. Han, J. H. Lee, S. M. Choi, H. S. Hwang, and C. W. Kim, IEEE Trans. Electron Devices, 52, 2654 (2005). https://doi.org/10.1109/TED.2005.859691
  6. H. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, IEEE Trans. Electron Devices, 37, 654 (1990). https://doi.org/10.1109/16.47770
  7. G. Groeseneken, H. E. Maes, J. V. Houdt, and J. S. Witters, Nonvolatile Semiconductor Memory Technology (IEEE Press, New York, 1998) p. 9.
  8. S. H. Bae, J. H. Lee, H. I. Kwon, J. R. Ahn, J. C. Om, C. H. Park, and J. H. Lee, IEEE Trans. Electron Devices, 56, 1624 (2009). https://doi.org/10.1109/TED.2009.2022700
  9. P. Magnone, F. Crupi, G. Giusi, C. Pace, E. Simoen, C. Claeys, L. Pantisano, D. Maji, V. R. Rao, and P. Srinivasan, IEEE Trans. Device & Mater. Reli.., 9, 180 (2009). https://doi.org/10.1109/TDMR.2009.2020406
  10. L. K. J. Vandamme, Solid State Electron., 28, 1049 (1985). https://doi.org/10.1016/0038-1101(85)90038-3
  11. A. Mercha, L. K. J. Vandamme, L. Pichon, R. Carin, and O. Bonnaud, J. Appl. Phys., 90, 4019 (2001). https://doi.org/10.1063/1.1404418
  12. L. Chen, J. Miao, L. Guo and R. Lin, Surf. Coat. Technol., 141, 96 (2001). https://doi.org/10.1016/S0257-8972(01)01163-X
  13. K. H. Lee, H. S. Kang, Y. S. Jang and S. K. Lim, Proc. 4th Int. Conf. on Solid State & IC Technol. (Beijing, China, 1995) p. 659.