• Proceedings of the KIEE Conference
• /
• 2004.11c
• /
• pp.212-214
• /
• 2004

Hardware implemented ring buffer systems and methods are presented for the effective management of the ring buffer in TCP/IP communication. The layer interface of the ring buffer systems transfer free buffer and used buffer size information to the TCP/IP stack upper or low layer. The pointer updation interface calculates a temporary pointer from the data size which is needed by the present pointer of the ring buffer and upper or lowyer layer. The pointer manager of the ring buffer systems is responsible for saving the present pointer of the ring buffer, updating the ring buffer pointer to the new pointer, calculating the free buffer size and used buffer size of the ring buffer, and transferring the information to the upper layer. The ring buffer systems help the TCP/IP layer and TCP/IP upper or lower layer to decide the sending or receiving data size effectively. The delay of transferring data can be lowered by the ring buffer system.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2015.08a
• /
• pp.147-147
• /
• 2015

The multilayer structure of the organic light emitting diode has merits of improving interfacial characteristics and helping carriers inject into emission layer and transport easier. There are many reports to control hole injection from anode electrode by using transition metal oxide as an anode buffer layer, such as V2O5, MoO3, NiO, and Fe3O4. In this study, we apply thin films of LiF which is usually inserted as a thin buffer layer between electron transport layer(ETL) and cathode, as an anode buffer layer to reduce the hole injection barrier height from ITO. The thickness of LiF as an anode buffer layer is tested from 0 nm to 1.0 nm. As shown in the figure 1 and 2, the luminous efficiency versus current density is improved by LiF anode buffer layer, and the threshold voltage is reduced when LiF buffer layer is increased up to 0.6 nm then the device does not work when LiF thickness is close to 1.0 nm As a result, we can confirm that the thin layer of LiF, about 0.6 nm, as an anode buffer reduces the hole injection barrier height from ITO, and this results the improved luminous efficiency. This study shows that LiF can be used as an anode buffer layer for improved hole injection as well as cathode buffer layer.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.02a
• /
• pp.91-91
• /
• 2011

박막태양전지의 높은 효율개선을 위해 TCO층과 p-layer 사이에 buffer layer를 넣어 Voc와 FF를 개선하는 연구가 진행되고 있다. 이에 buffer layer의 활성화 정도를 높이기 위해 p-layer을 최적화 시키고자한다. 이 실험에서 a-Si:B에 N2O를 도핑시켜 Bandgap Energy 2.0 eV, Activation Energy 0.4 eV인 a-SiOx:B 막을 제작하여 buffer layer로 사용하였고 이 buffer layer에 의한 cell의 효율 향상을 최적화 하기위해 ASA simulation을 이용해 p-layer의 Bandgap Energy와 Activation Energy를 가변 하여 보았다. 실험결과 p-layer의 Bandgap Energy 1.95 eV에서 buffer layer와 p-layer사이에서의 barrier가 최소가 됨을 확인 할 수 있었고 Actication Energy 0.5 eV에서 가장 높은 Voc를 가짐을 알 수 있었다. 본 연구를 통해 p-layer의 Bandgap Energy 1.95 eV, Activation Energy 0.5 eV에서 buffer layer를 활성화시키기 위한 p-layer의 최적화 조건을 구현해 볼 수 있었다.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.65 no.10
• /
• pp.1702-1705
• /
• 2016

We propose a novel hydrogen-reduced p-type amorphous silicon oxide buffer layer between $TiO_2$ antireflection layer and p-type silicon window layer of silicon thin film solar cells. This new buffer layer can protect underlying the $TiO_2$ by suppressing hydrogen plasma, which could be made by excluding $H_2$ gas introduction during plasma deposition. Amorphous silicon oxide thin film solar cells with employing the new buffer layer exhibited better conversion efficiency (8.10 %) compared with the standard cell (7.88 %) without the buffer layer. This new buffer layer can be processed in the same p-chamber with in-situ mode before depositing main p-type amorphous silicon oxide window layer. Comparing with state-of-the-art buffer layer of AZO/p-nc-SiOx:H, our new buffer layer can be processed with cost-effective, much simple process based on similar device performances.

• Korean Journal of Materials Research
• /
• v.19 no.3
• /
• pp.119-124
• /
• 2009

In the microelectronics packaging industry, the adhesion strength between Cu and polyimide and the thermal stability are very important factors, as they influence the performance and reliability of the device. The three different buffer layers of Cr, 50%Cr-50%Ni, and Ni were adopted in a Cu/buffer layer/polyimide system and compared in terms of their adhesion strength and thermal stability at a temperature of $300^{\circ}C$ for 24hrs. A 90-degree peel test and XPS analysis revealed that both the peel strength and thermal stability decreased in the order of the Cr, 50%Cr-50%Ni and Ni buffer layer. The XPS analysis revealed that Cu can diffuse through the thin Ni buffer layer ($200{\AA}$), resulting in a decrease in the adhesion strength when the Cu/buffer layer/polyimide multilayer is heat-treated at a temperature of $300^{\circ}C$ for 24hrs. In contrast, Cu did not diffuse through the Cr buffer layer under the same heat-treatment conditions.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2002.08a
• /
• pp.766-769
• /
• 2002

We have seen the effects of hole-injection buffer layer in organic light-emitting diodes using copper phthalocyanine(CuPc), poly(vinylcarbazole)(PVK), and Poly(3,4-ethylenedioxythiophene):poly(styrene-sulfonate)(PEDOT:PSS) in a device structure of ITO/buffer/TPD/$Alq_3$/Al. Polymer PVK and PEDOT:PSS buffer layer was made using spin casting method and the CuPc layer was made using thermal evaporation. Current-voltage characteristics, luminance-voltage characteristics and efficiency of device were measured at room temperature with a thickness variation of buffer layer. We have obtained an improvement of the external quantum efficiency by a factor of two, four, and two and half when the CuPc, PVK, and PEDOT:PSS buffer layer are used, respectively. The enhancement of the efficiency is attributed to the improved balance of holes and elelctrons due to the use of hole-injection buffer layer. The CuPc and PEDOT:PSS layer functions as a hole-injection supporter and the PVK layer as a hole-blocking one.

• Journal of the Korean Crystal Growth and Crystal Technology
• /
• v.10 no.1
• /
• pp.36-41
• /
• 2000

We studied the exchange anisotropy of Ni-Fe/Co-Fe/Mn-Ir/Cu/buffer/Si multilayers using D.C magnetron sputtering technique. Generally, Ni-Fe/Mn-Ir/buffer(Cu)/Si multilayers cannot pin the ferromagnetic layer for the lower exchange biased field. We got $H_{ex}$ ex/ increased by two times, after using Cu/Ta as buffer layer to get larger grain size of Mn-Ir layer and inserting very thin Co-Fe layer between the Ni-Fe layer and the Mn-Ir layer to get improved grain-to-grain epitaxy relation at the interface between Ni-Fe layer and Mn-Ir layer. The variation of $H_{ex}$ by thickness of Mn-Ir layer in ferromagnete/Mn-Ir/buffer/Si multilayers is different to that in Mn-Ir/ferromagnete/buffer/Si multilayers, because the volume distribution of grain size of Mn-Ir layer and the exchange energy at the interface between the Mn-Ir and the ferromagnetic layers is different for stacking sequence.

• Journal of the Korean Ceramic Society
• /
• v.52 no.4
• /
• pp.290-293
• /
• 2015

The properties of the IZTO thin films on the glass were studied with a variation of the $SiO_2$ buffer layer thickness. $SiO_2$ buffer layers were deposited by plasma-enhanced chemical vapor deposition (PECVD) on the glass, and the In-Zn-Tin-Oxide (IZTO) thin films were deposited on the buffer layer by RF magnetron sputtering. All the IZTO thin films with the $SiO_2$ buffer layer are shown to be amorphous. Optimum $SiO_2$ buffer layer thickness was obtained through analyzing the structural, morphological, electrical, and optical properties of the IZTO thin films. As a result, the IZTO surface roughness is 0.273 nm with a sheet resistance of $25.32{\Omega}/sq$ and the average transmittance is 82.51% in the visible region, at a $SiO_2$ buffer layer thickness of 40 nm. The result indicates that the uniformity of surface and the properties of the IZTO thin film on the glass were improved by employing the $SiO_2$ buffer layer and the IZTO thin film can be applied well to the transparent conductive oxide for display devices.

• The Korean Journal of Ceramics
• /
• v.3 no.3
• /
• pp.163-168
• /
• 1997

Most of heteroepitaxial $\beta$-SiC thin films have been successfully grown on Si(100) adapting a carburizing process, by which a few atomic layers of substrate surface is chemically converted to very thin SiC layer using hydrocarbon gas sources. Using an organo-silicon precursor, bis-trimethylsilymethane (BTMSM, [$C_7H_{20}Si_2$]), heteropitaxial $\beta$-SiC thin films were successfully grown directy on Si substrate without a carburized buffer layer. The defect density of the $\beta$-SiC thin films deposited without a carburized layer was as low as that of $\beta$-SiC films deposited on carburized buffer layer. In addition, void density was also reduced by the formation of self-buffer layer using BTMSM instead of carburized buffer layer. It seems to be mainly due to the characteristic bonding structure of BTMSM, in which Si-C was bonded alternately and tetrahedrally (SiC$_4$).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.06a
• /
• pp.261-262
• /
• 2006

High temperature superconducting coated conductor has multi-layer structure of protecting layer/superconducting layer/buffer layer/metallic substrate. The buffer layer consists of multi layer, and the architecture most widely used in RABiTS approach is $CeO_2$(cap layer)/YSZ(diffusion barrier layer)/$CeO_2$(seed layer). Multi-buffer layer deposition required many times and process. Therefore single buffer layer deposition study reduce 2G HTS manufacture efforts. Evaporation technique for single buffer deposition method is used for the $CeO_2$ layer. $CeO_2$ single buffer film could be achieved in the chamber. Detailed deposition conditions (temperature and partial gas pressure of deposition) were investigated for the rapid growth of high quality $CeO_2$ single buffer film.