• Journal of Ocean Engineering and Technology
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• v.11 no.1
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• pp.95-105
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• 1997

This paper presents a Inertial Measuring Unit(IMU) for motion measurement of an AUV. The IMU is composed of three parts: inertial sensors with three servo accelerometers and three rate gyros, an analog/digital interface board, and a signal processing board with TMS320C31 DSP processor. The IMU is a class of strap-down inwetial navigation system does not applicable directly to the navigation system in consequence of the AUV and integrated sensors for an integrated navigation system of the AUV. Fast calculstion of direction cosine matrix for the coordinate transformation body to reference is obtained through the DSP processor. A switching algotrithm is used to lessen the low frequency drift effect of the gyros in the vertical plane with use of low pass filtering of the signal of the accelerometers.

• Proceedings of the KIEE Conference
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• 1999.11b
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• pp.49-51
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• 1999

The direct thrust control of permanent magnet linear synchronous motor using digital signal processor (DSP) is presented. The motor self inductance, the initial flux linkage by the permanent magnet is calculated in advance by the finite element analysis. The equivalent circuit method and the digital signal processor are used for the simulation and experiment, respectively. The simulation and experimental results such as, thrust, current and speed responses to the commands are examined.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.5
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• pp.361-369
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• 1991

The optics and the signal processor of dual beam laser Doppler velocimeter(LDV) was fabricated. By using the dual beam and the forward scattering, the optics part of LDV was fabricated. And the signal processor of LDV was designed by the frequency counter type using new 11:6 period timing device in order to remove error signals, and was made of the reference clock of a 500 MHz ECL oscillator. Doppler frequencies from 10KHz to 70MHz can be measured using the signal processor. In the accuracy of the period counting part, from 1.81x10**-4% to 1.27% is estimated, and in the accuracy of the validation logic part, from 0.78% to 14.78% is estimated.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.8
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• pp.514-521
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• 2000

This paper presents a direct thrust control scheme for permanent magnet linear synchronous motor(PMLSM) by using digital signal processor(DSP). And a simulation method for the direct thrust control of a permanent magnet linear synchronous motor using the equivalent circuit is presented. The detent force that was obtained by cubic spline method is considered in the simulation. Thrust correction coefficient is utilized to estimate actual thrust on the direct thrust control, which considers the longitudinal end effect due to the finite core length of the permanent magnet linear synchronous motor. The motor self inductance, the initial flux linkage by the permanent magnet is calculated in advance by the finite element analysis, and then the direct control simulation is carried out. As the results, thrust, current and speed are shwon.

• Proceedings of the Korea Information Processing Society Conference
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• 2024.05a
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• pp.18-19
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• 2024

High Dynamic Range 는 디지털 카메라에 내장된 영상 보정 장치인 Image Signal Processor 의 주요 기능 중 하나로서, 영상의 밝고 어두운 정도의 범위를 넓혀, 피사체가 더 또렷하게 보이도록 한다. 초당 수십 프레임을 촬영하는 경우, 실시간 보정처리를 위해 ISP 에 사용되는 기능 및 알고리즘은 신속성과 효율성이 요구된다. 본 연구는 ISP 에 적합한 HDR 알고리즘을 선정을 목표로 하여, Histogram Equalization 과 Contrast Limited Adaptive Histogram Equalization 을 소개한다. 이어 해당 알고리즘들을 컴퓨터 프로그래밍으로 구현, CMOS 이미지 센서를 통해 추출한 raw image 를 보정하여 각 알고리즘의 성능을 검토하였다.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.4
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• pp.315-321
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• 2011

The CRT monitor display system for SONAR signal that are commonly used in ships or naval vessels uses vector scanning method. Therefore the processing circuits of the system is complex. Also because production had been shut down, the supply of parts is difficult as well as high-cost. FPGA -based embedded processor system is flexible to adapting to various applications because it makes simple processing circuits and its core is easily reconfigurable, and provides high speed performance in low-cost. In this paper, we describe an implementation of SONAR signal LCD display system using the FPGA embedded processor system to overcome some weakness of existing CRT system. By changing X-Y Deflection and CRT control blocks of current system into FPGA embedded processor system, our system provides the simplicity, flexibility and low-cost of system configuration, and also real-time acquisition and display of SONAR signal.

• Journal of Mechanical Science and Technology
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• v.16 no.11
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• pp.1379-1394
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• 2002

In case of a single input single output (SISO) system with a nonlinear term, a signal compression method is useful to identify a system because the equivalent impulse response of linear part from the system can be extracted by the method. However even though the signal compression method is useful to estimate uncertain parameters of the system, the method cannot be directly applied to a unique system with hysteresis characteristics because it cannot estimate all of the two different dynamic properties according to its motion direction. This paper proposes a signal compression method with a pre-processor to identify a unique system with two different dynamics according to its motion direction. The pre-processor plays a role of separating expansion and retraction properties from the system with hysteresis characteristics. For evaluating performance of the proposed approach, a simulation to estimate the assumed unknown parameters for an arbitrary known model is carried out. A motion platform with several single-rod cylinders is a representative unique system with two different dynamics, because each single-rod cylinder has expansion and retraction dynamic properties according to its motion direction. The nominal constant parameters of the motion platform are experimentally identified by using the proposed method. As its application, the identified parameters are applied to a design of a sliding mode controller for the simulator.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.5
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• pp.219-224
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• 2015

Recently, the multi-core processor architecture is widely used in the digital signal processors for enhancing its performance. Multi-core processors are classified either as symmetric or asymmetric. Asymmetric multi-core processors are known to have higher performance and more efficient than symmetric multi-core processors. In order to study the performance enhancement of asymmetric multi-core digital signal processors over the symmetric ones, the trace-driven simulation has been executed for various asymmetric quad-core, octa-core and hexadeca-core digital signal processors and compared with the symmetric ones of similar hardware budget using UTDSP benchmarks as input.

• Journal of the Institute of Convergence Signal Processing
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• v.17 no.1
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• pp.26-31
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• 2016

In this paper, we propose an image quality evaluation system for compact camera module and assess the effect of optical performance improvement for proposed anti-halation disk in small lens. We develop a image quality evaluation system for quality estimation of camera module image. And we also develop a program to control register in image signal processor. Finally the resolution, brightness, and color reproduction performances were evaluated image quality comparison between conventional and proposed camera module using developed quality evaluation system and ISP register control program.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.6
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• pp.1128-1133
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• 2008

Context-aware computing has been attracting the attention as an approach to alleviating the inconvenience in human-computer interactions. This paper proposes a context-aware system architecture to be implemented on an UoC (Ubiquitous system on Chip). A new proposed technology of CRS (Context Recognition Switch) and DOS (Dynamic and Optimal Standard) based on Context-awareness system architecture with pre-processor, HPSP(High Performance Signal Processor) in this paper. And proposed a new algorithm using in network topology processor shows for Ubiquitous Computing System. implementing in UoC (Ubiquitous System on Chip) base on the IEEE 802.15.4 WPAN (Wireless Personal Area Network) standard. Also, This context-aware based UoC architecture has been developed to apply to mobile intelligent robots which would support human in a context-aware manner.