• Title/Summary/Keyword: short-channel effects

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Analysis of short-shannel effect for doping concentration of DGMOSFET - On threshold Voltage (더블게이트MOSFET의 도핑농도에 따른 단채널 효과 분석 - 문턱전압을 중심으로)

  • Ko, Hyo-Geun;Han, Ji-Hyung;Jung, Hak-Kee
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.05a
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    • pp.731-733
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    • 2012
  • Because the Double gate MOSFET has two gates, it has more efficient on controling current than the exisiting MOSFET, and it can also decrease short channel effects in the nano-device. In this study, during the manufacturing the Double gate MOSFET, we will analyze the change of threshold voltage according to doping concentration that makes a significant impact on short channel effects. One of the structural factors that affect the threshold voltage on the Double gate MOSFET is the doping concentration, and it is very important device parameter. In this paper, we can find that the threshold voltage became larger when the doping concentration increased from $10^{15}cm^{-3}$ to $10^{19}cm^{-3}$.

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Design Consideration of Bulk FinFETs with Locally-Separated-Channel Structures for Sub-50 nm DRAM Cell Transistors

  • Jung, Han-A-Reum;Park, Ki-Heung;Lee, Jong-Ho
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.2
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    • pp.156-163
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    • 2008
  • We proposed a new $p^+/n^+$ gate locally-separated-channel (LSC) bulk FinFET which has vertically formed oxide region in the center of fin body, and device characteristics were optimized and compared with that of normal channel (NC) FinFET. Key device characteristics were investigated by changing length of $n^+$ poly-Si gate ($L_s$), the material filling the trench, and the width and length of the trench at a given gate length ($L_g$). Using 3-dimensional simulations, we confirmed that short-channel effects were properly suppressed although the fin width was the same as that of NC device. The LSC device having the trench non-overlapped with the source/drain diffusion region showed excellent $I_{off}$ suitable for sub-50 nm DRAM cell transistors. Design of the LSC devices were performed to get reasonable $L_s/L_g$ and channel fin width ($W_{cfin}$) at given $L_gs$ of 30 nm, 40 nm, and 50 nm.

Estimation of Effects of Underwater Acoustic Channel Capacity Due to the Bubbles in the High Frequency Near the Coastal Area

  • Zhou, Guoqing;Shim, Tae-Bo;Kim, Young-Gyu
    • The Journal of the Acoustical Society of Korea
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    • v.27 no.3E
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    • pp.69-76
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    • 2008
  • Measurements of bubble size and distribution in the surface layer of the sea, wind speed, and variation of ocean environments were made continually over a four-day period in an experiment conducted in the South Sea of Korea during 17-20 September 2007. Theoretical background of bubble population model indicates that bubble population is a function of the depth, range and wind speed and bubble effects on sound speed shows that sound speed varies with frequency. Observational evidence exhibited that the middle size bubble population fit the model very well, however, smaller ones can not follow the model probably due to their short lifetime. Meanwhile, there is also a hysteresis effect of void fraction. Observational evidence also indicates that strong changes in sound speed are produced by the presence of swarms of micro bubbles especially from 7 kHz to 50 kHz, and calculation results are consistent with the measured data in the high frequency band, but inconsistent in the low frequency band. Based on the measurements of the sound speed and high frequency transmission configuration in the bubble layer, we present an estimation of underwater acoustic channel capacity in the bubble layer.

Effects of Doping Concentration of Polycrystalline Silicon Gate Layer on Reliability Characteristics in MOSFET's (MOSFET에서 다결정 실리콘 게이트 막의 도핑 농도가 신뢰성에 미치는 영향)

  • Park, Keun-Hyung
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.31 no.2
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    • pp.74-79
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    • 2018
  • In this report, the results of a systematic study on the effects of polycrystalline silicon gate depletion on the reliability characteristics of metal-oxide semiconductor field-effect transistor (MOSFET) devices were discussed. The devices were fabricated using standard complimentary metal-oxide semiconductor (CMOS) processes, wherein phosphorus ion implantation with implant doses varying from $10^{13}$ to $5{\times}10^{15}cm^{-2}$ was performed to dope the polycrystalline silicon gate layer. For implant doses of $10^{14}/cm^2$ or less, the threshold voltage was increased with the formation of a depletion layer in the polycrystalline silicon gate layer. The gate-depletion effect was more pronounced for shorter channel lengths, like the narrow-width effect, which indicated that the gate-depletion effect could be used to solve the short-channel effect. In addition, the hot-carrier effects were significantly reduced for implant doses of $10^{14}/cm^2$ or less, which was attributed to the decreased gate current under the gate-depletion effects.

Analysis of Subthreshold Swing for Ratio of Channel Length and Thickness of Asymmetric Double Gate MOSFET (비대칭 DGMOSFET의 채널길이와 두께 비에 따른 문턱전압이하 스윙 분석)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.3
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    • pp.581-586
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    • 2015
  • This paper has analyzed the variation of subthreshold swing for the ratio of channel length and thickness for asymmetric double gate MOSFET. The asymmetric double gate MOSFET has the advantage that the factors to control the short channel effects increase since top and bottom gate structure can be fabricated differently. The degradation of transport property due to rapid increase of subthreshold swing can be specially reduced in the case of reduction of channel length. However, channel thickness has to be reduced for decrease of channel length from scaling theory. The ratio of channel length vs. thickness becomes the most important factor to determine subthreshold swing. To analyze hermeneutically subthreshold swing, the analytical potential distribution is derived from Poisson's equation, and conduction path and subthreshold swing are calculated for various channel length and thickness. As a result, we know conduction path and subthreshold swing are changed for the ratio of channel length vs. thickness.

Fabrication of wrap-around gate nanostructures from electrochemical deposition (전기화학적 도금을 이용한 wrap-around 게이트 나노구조의 제작)

  • Ahn, Jae-Hyun;Hong, Su-Heon;Kang, Myung-Gil;Hwang, Sung-Woo
    • Journal of IKEEE
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    • v.13 no.2
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    • pp.126-131
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    • 2009
  • To overcome short channel effects, wrap-around field effect transistors have drawn a great deal of attention for their superior electrostatic coupling between the channel and the surrounding gate electrode. In this paper, we introduce a bottom-up technique to fabricate a wrap-around field effect transistor using silicon nanowires as the conduction channel. Device fabrication was consisted mainly of electron-beam lithography, dielectrophoresis to accurately align the nanowires, and the formation of gate electrode using electrochemical deposition. The electrolyte for electrochemical deposition was made up of non-toxic organic-based solution and liquid nitrogen was used as a method of maintaining the shape of polymethyl methacrylate(PMMA) during the process of electrochemical deposition. Patterned PMMA can be used as a nano-template to produce wrap-around gate nano-structures.

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Design and Analysis of Sub-10 nm Junctionless Fin-Shaped Field-Effect Transistors

  • Kim, Sung Yoon;Seo, Jae Hwa;Yoon, Young Jun;Yoo, Gwan Min;Kim, Young Jae;Eun, Hye Rim;Kang, Hye Su;Kim, Jungjoon;Cho, Seongjae;Lee, Jung-Hee;Kang, In Man
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.5
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    • pp.508-517
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    • 2014
  • We design and analyze the n-channel junctionless fin-shaped field-effect transistor (JL FinFET) with 10-nm gate length and compare its performances with those of the conventional bulk-type fin-shaped FET (conventional bulk FinFET). A three-dimensional (3-D) device simulations were performed to optimize the device design parameters including the width ($W_{fin}$) and height ($H_{fin}$) of the fin as well as the channel doping concentration ($N_{ch}$). Based on the design optimization, the two devices were compared in terms of direct-current (DC) and radio-frequency (RF) characteristics. The results reveal that the JL FinFET has better subthreshold swing, and more effectively suppresses short-channel effects (SCEs) than the conventional bulk FinFET.

Doping Profile Dependent Subthreshold Swing for Double Gate MOSFET (DGMOSFET에서 문턱전압이하 스윙의 도핑분포 의존성)

  • Jung, Hak-Kee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.8
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    • pp.1764-1770
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    • 2011
  • In this paper, the subthreshold swings for doping distribution in the channel have been analyzed in double gate MOSFET(DGMOSFET). The DGMOSFET is extensively been studying since it can lessen the short channel effects(SCEs) as next -generation nano device. The degradation of subthreshold swing(SS) known as SCEs has greatly influenced on application of digital devices, and has been analyzed for structural parameter and variation of channel doping profile in DGMOSFET. The analytical model of Poisson equation has been derived from nonuniform doping distribution for DGMOSFET. To verify potential and subthreshold swing model based on this analytical Poisson's equation, the results have been compared with those of the numerical Poisson's equation, and subthreshold swing for DGMOSFET has been analyzed using these models.

Analysis of Subthreshold Characteristics for Double Gate MOSFET using Impact Factor based on Scaling Theory (스켈링이론에 가중치를 적용한 DGMOSFET의 문턱전압이하 특성 분석)

  • Jung, Hak-Kee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.9
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    • pp.2015-2020
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    • 2012
  • The subthreshold characteristics has been analyzed to investigate the effect of two gate in Double Gate MOSFET using impact factor based on scaling theory. The charge distribution of Gaussian function validated in previous researches has been used to obtain potential distribution in Poisson equation. The potential distribution was used to investigate the short channel effects such as threshold voltage roll-off, subthreshold swings and drain induced barrier lowering by varying impact factor for scaling factor. The impact factor of 0.1~1.0 for channel length and 1.0~2.0 for channel thickness are used to fit structural feature of DGMOSFET. The simulation result showed that the subthreshold swings are mostly effected by impact factor but are nearly constant for scaling factors. And threshold voltage roll-off and drain induced barrier lowering are also effected by both impact factor and scaling factor.

Threshold Voltage Roll-off for Bottom Gate Voltage of Asymmetric Double Gate MOSFET (비대칭 이중게이트 MOSFET의 하단게이트 전압에 따른 문턱전압이동현상)

  • Jung, Hakkee
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2014.05a
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    • pp.741-744
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    • 2014
  • This paper has analyzed threshold voltage roll-off for bottom gate voltages of asymmetric double gate(DG) MOSFET. Since the asymmetric DGMOSFET is four terminal device to be able to separately bias for top and bottom gates, the bottom gate voltage influences on threshold voltage. It is, therefore, investigated how the threshold voltage roll-off known as short channel effects is reduced with bottom gate voltage. In the pursuit of this purpose, off-current model is presented in the subthreshold region, and the threshold voltage roll-off is observed for channel length and thickness with a parameter of bottom gate voltage as threshold voltage is defined by top gate voltage that off-currnt is $10^{-7}A/{\mu}m$ per channel width. As a result to observe the threshold voltage roll-off for bottom gate voltage using this model, we know the bottom gate voltage greatly influences on threshold voltage roll-off voltages, especially in the region of short channel length and thickness.

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