• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4B
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• pp.162-169
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• 2005

Network traffic measurements show that the data traffic on packet switched networks has the self-similar features which is different from the traditional traffic models such as Poisson distribution or Markovian process model. Most of the call admission control researches have been done on the performance analysis of a single network switch. It is necessary to consider the performance analysis of the proposed admission control scheme under interconnected switch environment because the data traffic transmits through switches in networks. From the simulation results, it is shown that the call admission control scheme may not operate properly on the interconnected switch even though the scheme works well on a single switch. In this parer, we analyze the cell loss probability, utilization and self-similarity of output ports of the interconnected networks switch by using shared buffer memory management schemes and propose the new call admission control scheme considering the interconnected network switches under self-similar traffic environments.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.283-286
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• 2000

One major drawback of conventional output buffered switches is that the speed of writing cells into output buffer should be N times faster than input link speed. This paper proposes a new output buffer switch that divides one output buffer into several buffers and virtually shares the divided buffers by using a distributor. The proposed switch makes it possible to reduce the memory speed. The proposed switch is evaluated in terms of the average cell latency compared with the input buffered switches which use the arbitration alogorithms, i.e., iSLIP or wrapped wave front arbiter(WWFA).

• Journal of KIISE:Databases
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• v.35 no.6
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• pp.469-480
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• 2008

A shared disk (SD) cluster couples multiple nodes for high performance transaction processing, and all the coupled nodes share a common database at the disk level. To reduce the number of disk accesses, each node caches database pages in its memory buffer. Since a particular page may be cached simultaneously in different nodes, cache consistency should be maintained to ensure that nodes can always access the most recent version of database pages. Most cache consistency schemes proposed in the SD cluster adopted LRU as a buffer replacement algorithm. In this paper, we first present four buffer replacement algorithms that consider the characteristics of the SD cluster. Then we compare the performance of the buffer replacement algorithms. We perform the experiments on a variety of cluster configurations and database workloads. The experiment results show that the proposed algorithms achieve performance improvement up to 5 times of LRU algorithm.

• The Journal of Information Systems
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• v.6 no.1
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• pp.159-180
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• 1997

Database sharing system(DBSS) refers to a system for high performance transaction processing. In DBSS, the processing nodes are locally coupled via a high speed network and share a common database at the disk level. Each node has a local memory, a separate copy of operating system, and a DBMS. To reduce the number of disk accesses, the node caches database pages in its local memory buffer. However, since multiple nodes may be simultaneously cached a page, cache consistency must be ensured so that every node can always access the latest version of pages. In this paper, we propose efficient buffer invalidation schemes in DBSS, where the database is logically partitioned using primary copy authority to reduce locking overhead. The proposed schemes can improve performance by reducing the disk access overhead and the message overhead due to maintaining cache consistency. Furthermore, they can show good performance when database workloads are varied dynamically.

• The Transactions of the Korea Information Processing Society
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• v.5 no.1
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• pp.24-32
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• 1998

The bus contention among bus-based shared-memory multiprocessors limits their performance. In addition, under split bus transaction environment, multiprocessors may make some memory requests unnecessary stand by in the memory access buffer, which makes system performance worse. This unnecessary stand-by can be eliminated by maintaining the bitmap table which contains the status bit for each memory block. However, this mechanism requires a great size of SRAM for the status information, which is fully mapped from the whole memory blocks. To solve this problem, we propose a bitmap cache which exploits partial mapping and locality of references. The simulation results show that the proposed system can greatly reduce the capacity of SRAM for the status information with little deteriorating its performance.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.10
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• pp.24-33
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• 2001

Delay, delay variation and packet loss rate are principal QoS(Quality of Service) elements of packet communication. This paper proposes a new buffer allocation mechanism to improve the packet loss performance in such a situation that multiple logical buffers share a single physical memory buffer. In the proposed buffer allocation mechanism, the movement of dynamic threshold follows a curved track instead of a straight line which is used in the DT(dynamic threshold) mechanism. In order evaluate the effectiveness of the proposed mechanism, it is compared with the existing previously proposed mechanisms in several aspects including NC(no control), ST(Static Threshold) and DT mechanisms.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.4
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• pp.784-789
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• 2007

This paper presents an implementation of a new type of architecture to improve an overflow problem on the network buffer. Each receiver channel of network system stores the message in its own buffer. If some receiver channel receives many messages, buffer overflow problem may occur for the channel. This paper proposes a network controller that implements a receiver channel with shared-memory to save all of the received messages from the every incomming channels. The proposed architecture is applied to ARINC-429, a real-time control network for commercial avionics system. For verifying performance of the architecture, ARINC-429 controller is designed using a SOPC platform, designed by Verilog and targeted to Xilinx Virtex-4 with a built-in PPC405 core.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.80-90
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• 1996

The efficienty of ATM is based on the statical multiplexing of fixed-length packets, which are called cells. The most important technical point for realizing ATM switching network is an arrangement of the buffers and switches. Current most ATM switching networks are being achieved by using the switching modules based on the unit switch of $8{\times}8$ 150Mb/s or $16{\times}16$ 150Mb/s, the unit switch of $32{\times}32$150Mb/s for a large scale system is under study in many countries. In this paper, we proposed a new $32{\times}32$(4.9Gb/s throughput) ATM switch using Shared buffer memory switch which provides superior traffic characteristics in the cell loss, delay and throughput performance and easy LSI(Large Scale Integrated circuit). We analytically estimated and simulated by computer the buffer size into it. We also proposed the configuration of the large capacity ATM switching network($M{\times}M$.M>1,000) consisting of multistage to improve the link speed by non-blocking.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.7
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• pp.1497-1501
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• 2005

Branch instructions which make the sequential instruction flow changed cause pipeline stalls in microprocessor. The pipeline hazard due to branch instructions are the most serious problem that degrades the performance of microprocessors. Branch target buffer predicts whether a branch will be taken or not and supplies the address of the next instruction on the basis of that prediction. If the hanch target buffer predicts correctly, the instruction flow will not be stalled. This leads to the better performance of microprocessor. In this paper, the architecture of a ta8 memory that branch target buffer and TLB can share is presented. Because the two tag memories used for branch target buffer and TLB each is replaced by single combined tag memory, we can expect the smaller chip size and the faster prediction. This shared tag architecture is more advantageous for the microprocessors that uses more bits of address and exploits much more instruction level parallelism.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.527-528
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• 2008

In this paper, several cases of multi-shared bus architecture are discussed and in order to decrease the bridge latency, the architecture introducing a memory decoder is proposed. Finally, a LCD controller using DMA master is integrated in this bus architecture that is verified due to RTL simulation and FPGA board test. DMA, LCD line buffer and SDRAM controller are normally operated in the timing simulation using ModelSim tool, and the LCD image is confirmed in the real FPGA board containing LCD panel.